On Thu, Nov 6, 2014 at 8:44 AM, Felipe Balbi balbi@ti.com wrote:
BeagleBoard-X15 is the next generation Open Source Hardware BeagleBoard based on TI's AM5728 SoC featuring dual core 1.5GHZ A15 processor. The platform features 2GB DDR3L (w/dual 32bit busses), eSATA, 3 USB3.0 ports, integrated HDMI (1920x108@60), separate LCD port, video In port, 4GB eMMC, uSD, Analog audio in/out, dual 1G Ethernet.
For more information, refer to: http://www.elinux.org/Beagleboard:BeagleBoard-X15
Signed-off-by: Felipe Balbi balbi@ti.com Signed-off-by: Nishanth Menon nm@ti.com
awesome - looks good to me. Thanks for doing this.
changes since v1: new commit log
arch/arm/cpu/armv7/omap5/Kconfig | 4 + board/ti/beagle_x15/Kconfig | 12 ++ board/ti/beagle_x15/Makefile | 8 + board/ti/beagle_x15/board.c | 328 ++++++++++++++++++++++++++++++++++++++ board/ti/beagle_x15/mux_data.h | 55 +++++++ configs/beagle_x15_defconfig | 5 + include/configs/beagle_x15.h | 89 +++++++++++ include/configs/ti_omap5_common.h | 2 + 8 files changed, 503 insertions(+) create mode 100644 board/ti/beagle_x15/Kconfig create mode 100644 board/ti/beagle_x15/Makefile create mode 100644 board/ti/beagle_x15/board.c create mode 100644 board/ti/beagle_x15/mux_data.h create mode 100644 configs/beagle_x15_defconfig create mode 100644 include/configs/beagle_x15.h
diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 129982c..aca862d 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -12,6 +12,9 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX"
+config TARGET_BEAGLE_X15
bool "BeagleBoard X15"endchoice
config SYS_SOC @@ -20,5 +23,6 @@ config SYS_SOC source "board/compulab/cm_t54/Kconfig" source "board/ti/omap5_uevm/Kconfig" source "board/ti/dra7xx/Kconfig" +source "board/ti/beagle_x15/Kconfig"
endif diff --git a/board/ti/beagle_x15/Kconfig b/board/ti/beagle_x15/Kconfig new file mode 100644 index 0000000..a305ff1 --- /dev/null +++ b/board/ti/beagle_x15/Kconfig @@ -0,0 +1,12 @@ +if TARGET_BEAGLE_X15
+config SYS_BOARD
default "beagle_x15"+config SYS_VENDOR
default "ti"+config SYS_CONFIG_NAME
default "beagle_x15"+endif diff --git a/board/ti/beagle_x15/Makefile b/board/ti/beagle_x15/Makefile new file mode 100644 index 0000000..5cd6873 --- /dev/null +++ b/board/ti/beagle_x15/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2014 +# Texas Instruments, <www.ti.com> +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y := board.o diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c new file mode 100644 index 0000000..5cafc87 --- /dev/null +++ b/board/ti/beagle_x15/board.c @@ -0,0 +1,328 @@ +/*
- Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
- Author: Felipe Balbi balbi@ti.com
- Based on board/ti/dra7xx/evm.c
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <palmas.h> +#include <sata.h> +#include <usb.h> +#include <asm/omap_common.h> +#include <asm/emif.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sata.h> +#include <asm/arch/gpio.h> +#include <environment.h>
+#include "mux_data.h"
+#ifdef CONFIG_DRIVER_TI_CPSW +#include <cpsw.h> +#endif
+DECLARE_GLOBAL_DATA_PTR;
+const struct omap_sysinfo sysinfo = {
"Board: BeagleBoard x15\n"+};
+static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
.dmm_lisa_map_3 = 0x80740300,.is_ma_present = 0x1+};
+void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) +{
*dmm_lisa_regs = &beagle_x15_lisa_regs;+}
+static const struct emif_regs beagle_x15_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851B32, /* dont know what to do about this */.sdram_config = 0x61851B32,.sdram_config2 = 0x00000000,.ref_ctrl = 0x00001035,.sdram_tim1 = 0xCEEF266B,.sdram_tim2 = 0x328F7FDA,.sdram_tim3 = 0x027F88A8,.read_idle_ctrl = 0x00050001, /* not sure where in gel file */.zq_config = 0x0007190B,.temp_alert_config = 0x00000000,.emif_ddr_phy_ctlr_1_init = 0x0E24400A, /* not sure what to do about this */.emif_ddr_phy_ctlr_1 = 0x0E24400A, /* based on non hw level enabled */.emif_ddr_ext_phy_ctrl_1 = 0x10040100, /* not sure wherein gel file */.emif_ddr_ext_phy_ctrl_2 = 0x00740074,.emif_ddr_ext_phy_ctrl_3 = 0x00780078,.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,.emif_rd_wr_lvl_rmp_win = 0x00000000,.emif_rd_wr_lvl_rmp_ctl = 0x00000000, /* based on non hw level enabled */.emif_rd_wr_lvl_ctl = 0x00000000, /* not sure where based in gel file */.emif_rd_wr_exec_thresh = 0x00000305+};
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{
*regs = &beagle_x15_ddr3_532mhz_emif_regs;+}
+static const u32 beagle_x15_ddr3_ext_phy_ctrl_const_regs[] = {
0x00800080, // 60x00360036, // 70x00340034, // 80x00360036, // 90x00350035, // 100x00350035, // 110x01ff01ff, // 120x01ff01ff,0x01ff01ff,0x01ff01ff,0x01ff01ff,0x00430043,0x003e003e,0x004a004a,0x00470047,0x00400040,0x00000000,0x00600020,0x40010080,0x08102040,0x00400040,0x00400040,0x00400040,0x00400040,0x00400040+};
+void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size) +{
*regs = beagle_x15_ddr3_ext_phy_ctrl_const_regs;*size = ARRAY_SIZE(beagle_x15_ddr3_ext_phy_ctrl_const_regs);+}
+struct vcores_data beagle_x15_volts = {
.mpu.value = VDD_MPU_DRA752,.mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,.mpu.addr = TPS659038_REG_ADDR_SMPS12,.mpu.pmic = &tps659038,.eve.value = VDD_EVE_DRA752,.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,.eve.addr = TPS659038_REG_ADDR_SMPS45,.eve.pmic = &tps659038,.gpu.value = VDD_GPU_DRA752,.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,.gpu.addr = TPS659038_REG_ADDR_SMPS45,.gpu.pmic = &tps659038,.core.value = VDD_CORE_DRA752,.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,.core.addr = TPS659038_REG_ADDR_SMPS6,.core.pmic = &tps659038,.iva.value = VDD_IVA_DRA752,.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,.iva.addr = TPS659038_REG_ADDR_SMPS45,.iva.pmic = &tps659038,+};
+void hw_data_init(void) +{
*prcm = &dra7xx_prcm;*dplls_data = &dra7xx_dplls;*omap_vcores = &beagle_x15_volts;*ctrl = &dra7xx_ctrl;+}
+int board_init(void) +{
gpmc_init();gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);return 0;+}
+int board_late_init(void) +{
init_sata(0);/** DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds* This is the POWERHOLD-in-Low behavior.*/palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);return 0;+}
+static void do_set_mux32(u32 base,
struct pad_conf_entry const *array, int size)+{
int i;struct pad_conf_entry *pad = (struct pad_conf_entry *)array;for (i = 0; i < size; i++, pad++)writel(pad->val, base + pad->offset);+}
+void set_muxconf_regs_essential(void) +{
do_set_mux32((*ctrl)->control_padconf_core_base,core_padconf_array_essential,sizeof(core_padconf_array_essential) /sizeof(struct pad_conf_entry));+}
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{
omap_mmc_init(0, 0, 0, -1, -1);omap_mmc_init(1, 0, 0, -1, -1);return 0;+} +#endif
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{
/* break into full u-boot on 'c' */if (serial_tstc() && serial_getc() == 'c')return 1;+#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();env_relocate_spec();if (getenv_yesno("boot_os") != 1)return 1;+#endif
return 0;+} +#endif
+#ifdef CONFIG_DRIVER_TI_CPSW
+/* Delay value to add to calibrated value */ +#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8) +#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2) +#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0) +#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8) +#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2) +#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0) +#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
+static void cpsw_control(int enabled) +{
/* VTP can be added here */+}
+static struct cpsw_slave_data cpsw_slaves[] = {
{.slave_reg_ofs = 0x208,.sliver_reg_ofs = 0xd80,.phy_addr = 1,},{.slave_reg_ofs = 0x308,.sliver_reg_ofs = 0xdc0,.phy_addr = 2,},+};
+static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,.cpsw_base = CPSW_BASE,.mdio_div = 0xff,.channels = 8,.cpdma_reg_ofs = 0x800,.slaves = 1,.slave_data = cpsw_slaves,.ale_reg_ofs = 0xd00,.ale_entries = 1024,.host_port_reg_ofs = 0x108,.hw_stats_reg_ofs = 0x900,.bd_ram_ofs = 0x2000,.mac_control = (1 << 5),.control = cpsw_control,.host_port_num = 0,.version = CPSW_CTRL_VERSION_2,+};
+int board_eth_init(bd_t *bis) +{
int ret;uint8_t mac_addr[6];uint32_t mac_hi, mac_lo;uint32_t ctrl_val;/* try reading mac address from efuse */mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);mac_addr[0] = (mac_hi & 0xFF0000) >> 16;mac_addr[1] = (mac_hi & 0xFF00) >> 8;mac_addr[2] = mac_hi & 0xFF;mac_addr[3] = (mac_lo & 0xFF0000) >> 16;mac_addr[4] = (mac_lo & 0xFF00) >> 8;mac_addr[5] = mac_lo & 0xFF;if (!getenv("ethaddr")) {printf("<ethaddr> not set. Validating first E-fuse MAC\n");if (is_valid_ether_addr(mac_addr))eth_setenv_enetaddr("ethaddr", mac_addr);}mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);mac_addr[0] = (mac_hi & 0xFF0000) >> 16;mac_addr[1] = (mac_hi & 0xFF00) >> 8;mac_addr[2] = mac_hi & 0xFF;mac_addr[3] = (mac_lo & 0xFF0000) >> 16;mac_addr[4] = (mac_lo & 0xFF00) >> 8;mac_addr[5] = mac_lo & 0xFF;if (!getenv("eth1addr")) {if (is_valid_ether_addr(mac_addr))eth_setenv_enetaddr("eth1addr", mac_addr);}ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);ctrl_val |= 0x22;writel(ctrl_val, (*ctrl)->control_core_control_io1);ret = cpsw_register(&cpsw_data);if (ret < 0)printf("Error %d registering CPSW switch\n", ret);return ret;+} +#endif
+#ifdef CONFIG_USB_XHCI_OMAP +int board_usb_init(int index, enum usb_init_type init) +{
setbits_le32((*prcm)->cm_l3init_usb_otg_ss_clkctrl,OTG_SS_CLKCTRL_MODULEMODE_HW | OPTFCLKEN_REFCLK960M);return 0;+} +#endif diff --git a/board/ti/beagle_x15/mux_data.h b/board/ti/beagle_x15/mux_data.h new file mode 100644 index 0000000..2294abe --- /dev/null +++ b/board/ti/beagle_x15/mux_data.h @@ -0,0 +1,55 @@ +/*
- Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
- Author: Felipe Balbi balbi@ti.com
- Based on board/ti/dra7xx/evm.c
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _MUX_DATA_BEAGLE_X15_H_ +#define _MUX_DATA_BEAGLE_X15_H_
+#include <asm/arch/mux_dra7xx.h>
+const struct pad_conf_entry core_padconf_array_essential[] = {
{MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */{MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */{MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */{MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */{MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */{MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */{MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */{MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */{GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */{GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */{GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */{GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */{GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */{GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */{GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */{GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */{GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */{GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */{UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */{UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */{I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */{I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */{MDIO_MCLK, (PTU | PEN | M0)}, /* MDIO_MCLK */{MDIO_D, (IEN | PTU | PEN | M0)}, /* MDIO_D */{RGMII0_TXC, (M0) },{RGMII0_TXCTL, (M0) },{RGMII0_TXD3, (M0) },{RGMII0_TXD2, (M0) },{RGMII0_TXD1, (M0) },{RGMII0_TXD0, (M0) },{RGMII0_RXC, (IEN | M0) },{RGMII0_RXCTL, (IEN | M0) },{RGMII0_RXD3, (IEN | M0) },{RGMII0_RXD2, (IEN | M0) },{RGMII0_RXD1, (IEN | M0) },{RGMII0_RXD0, (IEN | M0) },{USB1_DRVVBUS, (M0 | FSC) },{SPI1_CS1, (PEN | IDIS | M14) }, /* GPIO7_11 */+}; +#endif /* _MUX_DATA_BEAGLE_X15_H_ */ diff --git a/configs/beagle_x15_defconfig b/configs/beagle_x15_defconfig new file mode 100644 index 0000000..872ab63 --- /dev/null +++ b/configs/beagle_x15_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=3" ++S:CONFIG_ARM=y ++S:CONFIG_OMAP54XX=y ++S:CONFIG_TARGET_BEAGLE_X15=y diff --git a/include/configs/beagle_x15.h b/include/configs/beagle_x15.h new file mode 100644 index 0000000..2009f5a --- /dev/null +++ b/include/configs/beagle_x15.h @@ -0,0 +1,89 @@ +/*
- (C) Copyright 2014
- Texas Instruments Incorporated.
- Felipe Balbi balbi@ti.com
- Configuration settings for the TI Beagle x15 board.
- See ti_omap5_common.h for omap5 common settings.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_BEAGLE_X15_H +#define __CONFIG_BEAGLE_X15_H
+#define CONFIG_AM57XX
+#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 2
+#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env"
+#define CONFIG_CMD_SAVEENV
+#define CONSOLEDEV "ttyO2" +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ +#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_OMAP_ABE_SYSCK
+/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"+#include <configs/ti_omap5_common.h>
+/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART
+/* CPSW Ethernet */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ +#define CONFIG_PHYLIB
+#define CONFIG_SUPPORT_EMMC_BOOT
+/* USB xHCI HOST */ +#define CONFIG_CMD_USB +#define CONFIG_USB_HOST +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
+#define CONFIG_OMAP_USB_PHY +#define CONFIG_OMAP_USB3PHY1_HOST
+/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)+#endif /* __CONFIG_BEAGLE_X5_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index de96d7d..c47651d 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -117,6 +117,8 @@ "setenv fdtfile dra7-evm.dtb; fi;" \ "if test $board_name = dra72x; then " \ "setenv fdtfile dra72-evm.dtb; fi;" \
"if test $board_name = beagle_x15; then " \"setenv fdtfile am57xx-beagle-x15.dtb; fi;" \ "if test $fdtfile = undefined; then " \ "echo WARNING: Could not determine device tree to use; fi; \0" \ "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \-- 2.1.0.GIT
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