For the DA8xx family of SoCs, the set_cpu_clk_info() function was not initialising the DSP frequency, leading to 'bdinfo' command output such as:
[...snip...] ARM frequency = 300 MHz DSP frequency = -536870913 MHz DDR frequency = 300 MHz
This commit provides a separate implementation of set_cpu_clk_info() for the DA8xx SoCs that initialises the DSP frequency to zero (since currently the DSP is not enabled by U-Boot on any DA8xx platform). The separate implementation is justified because there is no common code between DA8xx and the other SoC families. It is now much easier to understand the flow of the two separate functions.
Signed-off-by: Laurence Withers lwithers@guralp.com Cc: Tom Rini trini@ti.com Cc: Hadli, Manjunath manjunath.hadli@ti.com Cc: Heiko Schocher hs@denx.de --- Changes in v2: - Re-ordered patch series to tidy up clock IDs before tidying up users (set_cpu_clk_info()). --- arch/arm/cpu/arm926ejs/davinci/cpu.c | 23 ++++++++++++++--------- 1 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/cpu.c b/arch/arm/cpu/arm926ejs/davinci/cpu.c index 41201d0..b31add8 100644 --- a/arch/arm/cpu/arm926ejs/davinci/cpu.c +++ b/arch/arm/cpu/arm926ejs/davinci/cpu.c @@ -117,6 +117,17 @@ int clk_get(enum davinci_clk_ids id) out: return pll_out; } + +int set_cpu_clk_info(void) +{ + gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; + /* DDR PHY uses an x2 input clock */ + gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : + (clk_get(DAVINCI_DDR_CLKID) / 1000000); + gd->bd->bi_dsp_freq = 0; + return 0; +} + #else /* CONFIG_SOC_DA8XX */
static unsigned pll_div(volatile void *pllbase, unsigned offset) @@ -187,17 +198,9 @@ unsigned int davinci_clk_get(unsigned int div) return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; } #endif -#endif /* !CONFIG_SOC_DA8XX */
int set_cpu_clk_info(void) { -#ifdef CONFIG_SOC_DA8XX - gd->bd->bi_arm_freq = clk_get(DAVINCI_ARM_CLKID) / 1000000; - /* DDR PHY uses an x2 input clock */ - gd->bd->bi_ddr_freq = cpu_is_da830() ? 0 : - (clk_get(DAVINCI_DDR_CLKID) / 1000000); -#else - unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; #if defined(CONFIG_SOC_DM365) pllbase = DAVINCI_PLL_CNTRL1_BASE; @@ -216,10 +219,12 @@ int set_cpu_clk_info(void) pllbase = DAVINCI_PLL_CNTRL0_BASE; #endif gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; -#endif + return 0; }
+#endif /* !CONFIG_SOC_DA8XX */ + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init()