This does not use driver model and is more than two years past the migration date. Drop it.
It can be added back later if needed.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/arm/cpu/armv7/ls102xa/soc.c | 4 - arch/arm/include/asm/arch-ls102xa/config.h | 1 - board/freescale/common/Makefile | 2 - board/freescale/common/dcu_sii9022a.c | 248 ---------- board/freescale/common/dcu_sii9022a.h | 12 - board/freescale/ls1021aiot/Makefile | 1 - board/freescale/ls1021aiot/dcu.c | 48 -- board/freescale/ls1021aqds/Makefile | 1 - board/freescale/ls1021aqds/dcu.c | 110 ----- board/freescale/ls1021atwr/Makefile | 1 - board/freescale/ls1021atwr/dcu.c | 48 -- board/toradex/colibri_vf/Makefile | 1 - board/toradex/colibri_vf/colibri_vf.c | 62 --- board/toradex/colibri_vf/dcu.c | 38 -- configs/colibri_vf_defconfig | 1 - drivers/video/Kconfig | 15 - drivers/video/Makefile | 1 - drivers/video/fsl_dcu_fb.c | 548 --------------------- include/configs/colibri_vf.h | 7 - include/configs/ls1021aqds.h | 10 - include/configs/ls1021atwr.h | 13 - include/fsl_dcu_fb.h | 22 - scripts/config_whitelist.txt | 3 - 23 files changed, 1197 deletions(-) delete mode 100644 board/freescale/common/dcu_sii9022a.c delete mode 100644 board/freescale/common/dcu_sii9022a.h delete mode 100644 board/freescale/ls1021aiot/dcu.c delete mode 100644 board/freescale/ls1021aqds/dcu.c delete mode 100644 board/freescale/ls1021atwr/dcu.c delete mode 100644 board/toradex/colibri_vf/dcu.c delete mode 100644 drivers/video/fsl_dcu_fb.c delete mode 100644 include/fsl_dcu_fb.h
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 8a95ee86a9b..f5e4bd4bc0c 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -172,10 +172,6 @@ int arch_soc_init(void) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif
-#ifdef CONFIG_VIDEO_FSL_DCU_FB - out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); -#endif - /* Configure Little endian for SAI, ASRC and SPDIF */ out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 0e1f9e0c0d8..50e9d08f323 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -93,7 +93,6 @@ #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_DCU_BE #define CONFIG_SYS_FSL_SEC_MON_LE #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SFP_BE diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 0ddfb59d7de..c8f62bfc198 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -52,8 +52,6 @@ else obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o endif
-obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o - obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o
obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o diff --git a/board/freescale/common/dcu_sii9022a.c b/board/freescale/common/dcu_sii9022a.c deleted file mode 100644 index 9137d246ea0..00000000000 --- a/board/freescale/common/dcu_sii9022a.c +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - */ - -#include <asm/io.h> -#include <common.h> -#include <fsl_dcu_fb.h> -#include <i2c.h> -#include <linux/fb.h> - -#define PIXEL_CLK_LSB_REG 0x00 -#define PIXEL_CLK_MSB_REG 0x01 -#define VERT_FREQ_LSB_REG 0x02 -#define VERT_FREQ_MSB_REG 0x03 -#define TOTAL_PIXELS_LSB_REG 0x04 -#define TOTAL_PIXELS_MSB_REG 0x05 -#define TOTAL_LINES_LSB_REG 0x06 -#define TOTAL_LINES_MSB_REG 0x07 -#define TPI_INBUS_FMT_REG 0x08 -#define TPI_INPUT_FMT_REG 0x09 -#define TPI_OUTPUT_FMT_REG 0x0A -#define TPI_SYS_CTRL_REG 0x1A -#define TPI_PWR_STAT_REG 0x1E -#define TPI_AUDIO_HANDING_REG 0x25 -#define TPI_AUDIO_INTF_REG 0x26 -#define TPI_AUDIO_FREQ_REG 0x27 -#define TPI_SET_PAGE_REG 0xBC -#define TPI_SET_OFFSET_REG 0xBD -#define TPI_RW_ACCESS_REG 0xBE -#define TPI_TRANS_MODE_REG 0xC7 - -#define TPI_INBUS_CLOCK_RATIO_1 (1 << 6) -#define TPI_INBUS_FULL_PIXEL_WIDE (1 << 5) -#define TPI_INBUS_RISING_EDGE (1 << 4) -#define TPI_INPUT_CLR_DEPTH_8BIT (0 << 6) -#define TPI_INPUT_VRANGE_EXPAN_AUTO (0 << 2) -#define TPI_INPUT_CLR_RGB (0 << 0) -#define TPI_OUTPUT_CLR_DEPTH_8BIT (0 << 6) -#define TPI_OUTPUT_VRANGE_COMPRE_AUTO (0 << 2) -#define TPI_OUTPUT_CLR_HDMI_RGB (0 << 0) -#define TPI_SYS_TMDS_OUTPUT (0 << 4) -#define TPI_SYS_AV_NORAML (0 << 3) -#define TPI_SYS_AV_MUTE (1 << 3) -#define TPI_SYS_DVI_MODE (0 << 0) -#define TPI_SYS_HDMI_MODE (1 << 0) -#define TPI_PWR_STAT_MASK (3 << 0) -#define TPI_PWR_STAT_D0 (0 << 0) -#define TPI_AUDIO_PASS_BASIC (0 << 0) -#define TPI_AUDIO_INTF_I2S (2 << 6) -#define TPI_AUDIO_INTF_NORMAL (0 << 4) -#define TPI_AUDIO_TYPE_PCM (1 << 0) -#define TPI_AUDIO_SAMP_SIZE_16BIT (1 << 6) -#define TPI_AUDIO_SAMP_FREQ_44K (2 << 3) -#define TPI_SET_PAGE_SII9022A 0x01 -#define TPI_SET_OFFSET_SII9022A 0x82 -#define TPI_RW_EN_SRC_TERMIN (1 << 0) -#define TPI_TRANS_MODE_ENABLE (0 << 7) - -/* Programming of Silicon SIi9022a HDMI Transmitter */ -int dcu_set_dvi_encoder(struct fb_videomode *videomode) -{ - u8 temp; - u16 temp1, temp2; - u32 temp3; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - int ret; - - ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM, - CONFIG_SYS_I2C_DVI_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - CONFIG_SYS_I2C_DVI_BUS_NUM); - return ret; - } - - /* Enable TPI transmitter mode */ - temp = TPI_TRANS_MODE_ENABLE; - dm_i2c_write(dev, TPI_TRANS_MODE_REG, &temp, 1); - - /* Enter into D0 state, full operation */ - dm_i2c_read(dev, TPI_PWR_STAT_REG, &temp, 1); - temp &= ~TPI_PWR_STAT_MASK; - temp |= TPI_PWR_STAT_D0; - dm_i2c_write(dev, TPI_PWR_STAT_REG, &temp, 1); - - /* Enable source termination */ - temp = TPI_SET_PAGE_SII9022A; - dm_i2c_write(dev, TPI_SET_PAGE_REG, &temp, 1); - temp = TPI_SET_OFFSET_SII9022A; - dm_i2c_write(dev, TPI_SET_OFFSET_REG, &temp, 1); - - dm_i2c_read(dev, TPI_RW_ACCESS_REG, &temp, 1); - temp |= TPI_RW_EN_SRC_TERMIN; - dm_i2c_write(dev, TPI_RW_ACCESS_REG, &temp, 1); - - /* Set TPI system control */ - temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE; - dm_i2c_write(dev, TPI_SYS_CTRL_REG, &temp, 1); - - /* Set pixel clock */ - temp1 = PICOS2KHZ(videomode->pixclock) / 10; - temp = (u8)(temp1 & 0xFF); - dm_i2c_write(dev, PIXEL_CLK_LSB_REG, &temp, 1); - temp = (u8)(temp1 >> 8); - dm_i2c_write(dev, PIXEL_CLK_MSB_REG, &temp, 1); - - /* Set total pixels per line */ - temp1 = videomode->hsync_len + videomode->left_margin + - videomode->xres + videomode->right_margin; - temp = (u8)(temp1 & 0xFF); - dm_i2c_write(dev, TOTAL_PIXELS_LSB_REG, &temp, 1); - temp = (u8)(temp1 >> 8); - dm_i2c_write(dev, TOTAL_PIXELS_MSB_REG, &temp, 1); - - /* Set total lines */ - temp2 = videomode->vsync_len + videomode->upper_margin + - videomode->yres + videomode->lower_margin; - temp = (u8)(temp2 & 0xFF); - dm_i2c_write(dev, TOTAL_LINES_LSB_REG, &temp, 1); - temp = (u8)(temp2 >> 8); - dm_i2c_write(dev, TOTAL_LINES_MSB_REG, &temp, 1); - - /* Set vertical frequency in Hz */ - temp3 = temp1 * temp2; - temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3; - temp1 = (u16)temp3 * 100; - temp = (u8)(temp1 & 0xFF); - dm_i2c_write(dev, VERT_FREQ_LSB_REG, &temp, 1); - temp = (u8)(temp1 >> 8); - dm_i2c_write(dev, VERT_FREQ_MSB_REG, &temp, 1); - - /* Set TPI input bus and pixel repetition data */ - temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE | - TPI_INBUS_RISING_EDGE; - dm_i2c_write(dev, TPI_INBUS_FMT_REG, &temp, 1); - - /* Set TPI AVI Input format data */ - temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO | - TPI_INPUT_CLR_RGB; - dm_i2c_write(dev, TPI_INPUT_FMT_REG, &temp, 1); - - /* Set TPI AVI Output format data */ - temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO | - TPI_OUTPUT_CLR_HDMI_RGB; - dm_i2c_write(dev, TPI_OUTPUT_FMT_REG, &temp, 1); - - /* Set TPI audio configuration write data */ - temp = TPI_AUDIO_PASS_BASIC; - dm_i2c_write(dev, TPI_AUDIO_HANDING_REG, &temp, 1); - - temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL | - TPI_AUDIO_TYPE_PCM; - dm_i2c_write(dev, TPI_AUDIO_INTF_REG, &temp, 1); - - temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K; - dm_i2c_write(dev, TPI_AUDIO_FREQ_REG, &temp, 1); -#else - i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); - - /* Enable TPI transmitter mode */ - temp = TPI_TRANS_MODE_ENABLE; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, &temp, 1); - - /* Enter into D0 state, full operation */ - i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1); - temp &= ~TPI_PWR_STAT_MASK; - temp |= TPI_PWR_STAT_D0; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1); - - /* Enable source termination */ - temp = TPI_SET_PAGE_SII9022A; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, &temp, 1); - temp = TPI_SET_OFFSET_SII9022A; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, &temp, 1); - - i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1); - temp |= TPI_RW_EN_SRC_TERMIN; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1); - - /* Set TPI system control */ - temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, &temp, 1); - - /* Set pixel clock */ - temp1 = PICOS2KHZ(videomode->pixclock) / 10; - temp = (u8)(temp1 & 0xFF); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_LSB_REG, 1, &temp, 1); - temp = (u8)(temp1 >> 8); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_MSB_REG, 1, &temp, 1); - - /* Set total pixels per line */ - temp1 = videomode->hsync_len + videomode->left_margin + - videomode->xres + videomode->right_margin; - temp = (u8)(temp1 & 0xFF); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_LSB_REG, 1, &temp, 1); - temp = (u8)(temp1 >> 8); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_MSB_REG, 1, &temp, 1); - - /* Set total lines */ - temp2 = videomode->vsync_len + videomode->upper_margin + - videomode->yres + videomode->lower_margin; - temp = (u8)(temp2 & 0xFF); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_LSB_REG, 1, &temp, 1); - temp = (u8)(temp2 >> 8); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_MSB_REG, 1, &temp, 1); - - /* Set vertical frequency in Hz */ - temp3 = temp1 * temp2; - temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3; - temp1 = (u16)temp3 * 100; - temp = (u8)(temp1 & 0xFF); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_LSB_REG, 1, &temp, 1); - temp = (u8)(temp1 >> 8); - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_MSB_REG, 1, &temp, 1); - - /* Set TPI input bus and pixel repetition data */ - temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE | - TPI_INBUS_RISING_EDGE; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INBUS_FMT_REG, 1, &temp, 1); - - /* Set TPI AVI Input format data */ - temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO | - TPI_INPUT_CLR_RGB; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INPUT_FMT_REG, 1, &temp, 1); - - /* Set TPI AVI Output format data */ - temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO | - TPI_OUTPUT_CLR_HDMI_RGB; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_OUTPUT_FMT_REG, 1, &temp, 1); - - /* Set TPI audio configuration write data */ - temp = TPI_AUDIO_PASS_BASIC; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_HANDING_REG, 1, &temp, 1); - - temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL | - TPI_AUDIO_TYPE_PCM; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_INTF_REG, 1, &temp, 1); - - temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K; - i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1); -#endif - - return 0; -} diff --git a/board/freescale/common/dcu_sii9022a.h b/board/freescale/common/dcu_sii9022a.h deleted file mode 100644 index 7851775530d..00000000000 --- a/board/freescale/common/dcu_sii9022a.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __DCU_HDMI_SII9022A__ -#define __DCU_HDMI_SII9022A__ - -/* Programming of Silicon SII9022A connector HDMI Transmitter*/ -int dcu_set_dvi_encoder(struct fb_videomode *videomode); - -#endif diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile index bec151fd2ac..587bbd79ddf 100644 --- a/board/freescale/ls1021aiot/Makefile +++ b/board/freescale/ls1021aiot/Makefile @@ -3,5 +3,4 @@ # Copyright 2016 Freescale Semiconductor, Inc.
obj-y += ls1021aiot.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c deleted file mode 100644 index e4fbcbcaad3..00000000000 --- a/board/freescale/ls1021aiot/dcu.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - * - * FSL DCU Framebuffer driver - */ - -#include <common.h> -#include <fsl_dcu_fb.h> -#include <asm/global_data.h> -#include "div64.h" -#include "../common/dcu_sii9022a.h" - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int dcu_set_pixel_clock(unsigned int pixclock) -{ - unsigned long long div; - - div = (unsigned long long)(gd->bus_clk / 1000); - div *= (unsigned long long)pixclock; - do_div(div, 1000000000); - - return div; -} - -int platform_dcu_init(struct fb_info *fbinfo, - unsigned int xres, unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode) -{ - const char *name; - unsigned int pixel_format; - - if (strncmp(port, "twr_lcd", 4) == 0) { - name = "TWR_LCD_RGB card"; - } else { - name = "HDMI"; - dcu_set_dvi_encoder(dcu_fb_videomode); - } - - printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); - - pixel_format = 32; - fsl_dcu_init(fbinfo, xres, yres, pixel_format); - - return 0; -} diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index 1e50e468a32..65030342be3 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -7,5 +7,4 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/dcu.c b/board/freescale/ls1021aqds/dcu.c deleted file mode 100644 index b5fee06b5b0..00000000000 --- a/board/freescale/ls1021aqds/dcu.c +++ /dev/null @@ -1,110 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP - * - * FSL DCU Framebuffer driver - */ - -#include <asm/global_data.h> -#include <asm/io.h> -#include <common.h> -#include <fsl_dcu_fb.h> -#include <i2c.h> -#include "../common/i2c_mux.h" -#include "div64.h" -#include "../common/diu_ch7301.h" -#include "ls1021aqds_qixis.h" - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int dcu_set_pixel_clock(unsigned int pixclock) -{ - unsigned long long div; - - div = (unsigned long long)(gd->bus_clk / 1000); - div *= (unsigned long long)pixclock; - do_div(div, 1000000000); - - return div; -} - -int platform_dcu_init(struct fb_info *fbinfo, - unsigned int xres, - unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode) -{ - const char *name; - unsigned int pixel_format; - int ret; - u8 ch; - - /* Mux I2C3+I2C4 as HSYNC+VSYNC */ -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - /* QIXIS device mount on I2C1 bus*/ - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR, - 1, &dev); - if (ret) { - printf("%s: Cannot find udev for a bus %d\n", __func__, - 0); - return ret; - } - ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1); - if (ret) { - printf("Error: failed to read I2C @%02x\n", - CONFIG_SYS_I2C_QIXIS_ADDR); - return ret; - } - ch &= 0x1F; - ch |= 0xA0; - ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1); - -#else - ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, - 1, &ch, 1); - if (ret) { - printf("Error: failed to read I2C @%02x\n", - CONFIG_SYS_I2C_QIXIS_ADDR); - return ret; - } - ch &= 0x1F; - ch |= 0xA0; - ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5, - 1, &ch, 1); -#endif - if (ret) { - printf("Error: failed to write I2C @%02x\n", - CONFIG_SYS_I2C_QIXIS_ADDR); - return ret; - } - - if (strncmp(port, "hdmi", 4) == 0) { - unsigned long pixval; - - name = "HDMI"; - - pixval = 1000000000 / dcu_fb_videomode->pixclock; - pixval *= 1000; - -#if !CONFIG_IS_ENABLED(DM_I2C) - i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM); -#endif - select_i2c_ch_pca9547(I2C_MUX_CH_CH7301, - CONFIG_SYS_I2C_DVI_BUS_NUM); - diu_set_dvi_encoder(pixval); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, - CONFIG_SYS_I2C_DVI_BUS_NUM); - } else { - return 0; - } - - printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); - - pixel_format = 32; - fsl_dcu_init(fbinfo, xres, yres, pixel_format); - - return 0; -} diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile index d9a2f52f2b6..cfa6c0c8540 100644 --- a/board/freescale/ls1021atwr/Makefile +++ b/board/freescale/ls1021atwr/Makefile @@ -5,5 +5,4 @@ #
obj-y += ls1021atwr.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c deleted file mode 100644 index 7bf283e3d66..00000000000 --- a/board/freescale/ls1021atwr/dcu.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * FSL DCU Framebuffer driver - */ - -#include <common.h> -#include <fsl_dcu_fb.h> -#include <asm/global_data.h> -#include "div64.h" -#include "../common/dcu_sii9022a.h" - -DECLARE_GLOBAL_DATA_PTR; - -unsigned int dcu_set_pixel_clock(unsigned int pixclock) -{ - unsigned long long div; - - div = (unsigned long long)(gd->bus_clk / 1000); - div *= (unsigned long long)pixclock; - do_div(div, 1000000000); - - return div; -} - -int platform_dcu_init(struct fb_info *fbinfo, - unsigned int xres, unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode) -{ - const char *name; - unsigned int pixel_format; - - if (strncmp(port, "twr_lcd", 4) == 0) { - name = "TWR_LCD_RGB card"; - } else { - name = "HDMI"; - dcu_set_dvi_encoder(dcu_fb_videomode); - } - - printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); - - pixel_format = 32; - fsl_dcu_init(fbinfo, xres, yres, pixel_format); - - return 0; -} diff --git a/board/toradex/colibri_vf/Makefile b/board/toradex/colibri_vf/Makefile index 6272a774963..9be2cbc037b 100644 --- a/board/toradex/colibri_vf/Makefile +++ b/board/toradex/colibri_vf/Makefile @@ -3,4 +3,3 @@ # Copyright 2013 Freescale Semiconductor, Inc.
obj-y := colibri_vf.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index c09591e5436..dcef2db360a 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -19,7 +19,6 @@ #include <asm/io.h> #include <env.h> #include <fdt_support.h> -#include <fsl_dcu_fb.h> #include <g_dnl.h> #include <jffs2/load_kernel.h> #include <mtd_node.h> @@ -205,49 +204,6 @@ static void setup_iomux_gpio(void) } #endif
-#ifdef CONFIG_VIDEO_FSL_DCU_FB -static void setup_iomux_fsl_dcu(void) -{ - static const iomux_v3_cfg_t dcu0_pads[] = { - VF610_PAD_PTE0__DCU0_HSYNC, - VF610_PAD_PTE1__DCU0_VSYNC, - VF610_PAD_PTE2__DCU0_PCLK, - VF610_PAD_PTE4__DCU0_DE, - VF610_PAD_PTE5__DCU0_R0, - VF610_PAD_PTE6__DCU0_R1, - VF610_PAD_PTE7__DCU0_R2, - VF610_PAD_PTE8__DCU0_R3, - VF610_PAD_PTE9__DCU0_R4, - VF610_PAD_PTE10__DCU0_R5, - VF610_PAD_PTE11__DCU0_R6, - VF610_PAD_PTE12__DCU0_R7, - VF610_PAD_PTE13__DCU0_G0, - VF610_PAD_PTE14__DCU0_G1, - VF610_PAD_PTE15__DCU0_G2, - VF610_PAD_PTE16__DCU0_G3, - VF610_PAD_PTE17__DCU0_G4, - VF610_PAD_PTE18__DCU0_G5, - VF610_PAD_PTE19__DCU0_G6, - VF610_PAD_PTE20__DCU0_G7, - VF610_PAD_PTE21__DCU0_B0, - VF610_PAD_PTE22__DCU0_B1, - VF610_PAD_PTE23__DCU0_B2, - VF610_PAD_PTE24__DCU0_B3, - VF610_PAD_PTE25__DCU0_B4, - VF610_PAD_PTE26__DCU0_B5, - VF610_PAD_PTE27__DCU0_B6, - VF610_PAD_PTE28__DCU0_B7, - }; - - imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads)); -} - -static void setup_tcon(void) -{ - setbits_le32(TCON0_BASE_ADDR, (1 << 29)); -} -#endif - static inline int is_colibri_vf61(void) { struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR; @@ -353,11 +309,6 @@ static void clock_init(void) CCM_CSCDR3_NFC_PRE_DIV(3)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(2)); - -#ifdef CONFIG_VIDEO_FSL_DCU_FB - setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK); - setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK); -#endif }
static void mscm_init(void) @@ -378,11 +329,6 @@ int board_early_init_f(void) setup_iomux_gpio(); #endif
-#ifdef CONFIG_VIDEO_FSL_DCU_FB - setup_tcon(); - setup_iomux_fsl_dcu(); -#endif - return 0; }
@@ -433,9 +379,6 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { -#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO) - int ret = 0; -#endif #ifdef CONFIG_FDT_FIXUP_PARTITIONS static const struct node_info nodes[] = { { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */ @@ -445,11 +388,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) puts(" Updating MTD partitions...\n"); fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); #endif -#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO) - ret = fsl_dcu_fixedfb_setup(blob); - if (ret) - return ret; -#endif
return ft_common_board_setup(blob, bd); } diff --git a/board/toradex/colibri_vf/dcu.c b/board/toradex/colibri_vf/dcu.c deleted file mode 100644 index c688ed79ffd..00000000000 --- a/board/toradex/colibri_vf/dcu.c +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2017 Toradex AG - * - * FSL DCU platform driver - */ - -#include <asm/arch/crm_regs.h> -#include <asm/io.h> -#include <common.h> -#include <fsl_dcu_fb.h> -#include "div64.h" - -unsigned int dcu_set_pixel_clock(unsigned int pixclock) -{ - struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; - unsigned long long div; - - clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL); - clrsetbits_le32(&ccm->cscdr3, - CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN, - CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN); - div = (unsigned long long)(PLL1_PFD2_FREQ / 1000); - do_div(div, pixclock); - - return div; -} - -int platform_dcu_init(struct fb_info *fbinfo, - unsigned int xres, - unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode) -{ - fsl_dcu_init(fbinfo, xres, yres, 32); - - return 0; -} diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig index 350e1cf30e4..6afe9e0bfa5 100644 --- a/configs/colibri_vf_defconfig +++ b/configs/colibri_vf_defconfig @@ -102,7 +102,6 @@ CONFIG_DM_VIDEO=y CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP8 is not set # CONFIG_VIDEO_BPP16 is not set -CONFIG_VIDEO_FSL_DCU_FB=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 51570310533..e74a3dd9285 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -601,21 +601,6 @@ config VIDEO_IVYBRIDGE_IGD a special tool which configures the VGA ROM, but the graphics resolution can be selected in U-Boot.
-config VIDEO_FSL_DCU_FB - bool "Enable Freescale Display Control Unit" - depends on VIDEO || DM_VIDEO - help - This enables support for Freescale Display Control Unit (DCU4) - module found on Freescale Vybrid and QorIQ family of SoCs. - -config VIDEO_FSL_DCU_MAX_FB_SIZE_MB - int "Freescale DCU framebuffer size" - depends on VIDEO_FSL_DCU_FB - default 4194304 - help - Set maximum framebuffer size to be used for Freescale Display - Controller Unit (DCU4). - source "drivers/video/rockchip/Kconfig"
config VIDEO_ARM_MALIDP diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 18d53e5803c..656b981ca9d 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -49,7 +49,6 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o obj-$(CONFIG_VIDEO_EFI) += efi.o -obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += imx/ obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c deleted file mode 100644 index b8bd4727c96..00000000000 --- a/drivers/video/fsl_dcu_fb.c +++ /dev/null @@ -1,548 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 Toradex AG - * - * FSL DCU Framebuffer driver - */ - -#include <init.h> -#include <asm/cache.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <common.h> -#include <dm.h> -#include <fdt_support.h> -#include <fsl_dcu_fb.h> -#include <linux/fb.h> -#include <malloc.h> -#include <video.h> -#include "videomodes.h" - -/* Convert the X,Y resolution pair into a single number */ -#define RESOLUTION(x, y) (((u32)(x) << 16) | (y)) - -#ifdef CONFIG_SYS_FSL_DCU_LE -#define dcu_read32 in_le32 -#define dcu_write32 out_le32 -#elif defined(CONFIG_SYS_FSL_DCU_BE) -#define dcu_read32 in_be32 -#define dcu_write32 out_be32 -#endif - -#define DCU_MODE_BLEND_ITER(x) ((x) << 20) -#define DCU_MODE_RASTER_EN (1 << 14) -#define DCU_MODE_NORMAL 1 -#define DCU_MODE_COLORBAR 3 -#define DCU_BGND_R(x) ((x) << 16) -#define DCU_BGND_G(x) ((x) << 8) -#define DCU_BGND_B(x) (x) -#define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) -#define DCU_DISP_SIZE_DELTA_X(x) (x) -#define DCU_HSYN_PARA_BP(x) ((x) << 22) -#define DCU_HSYN_PARA_PW(x) ((x) << 11) -#define DCU_HSYN_PARA_FP(x) (x) -#define DCU_VSYN_PARA_BP(x) ((x) << 22) -#define DCU_VSYN_PARA_PW(x) ((x) << 11) -#define DCU_VSYN_PARA_FP(x) (x) -#define DCU_SYN_POL_INV_PXCK_FALL (1 << 6) -#define DCU_SYN_POL_NEG_REMAIN (0 << 5) -#define DCU_SYN_POL_INV_VS_LOW (1 << 1) -#define DCU_SYN_POL_INV_HS_LOW (1) -#define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) -#define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) -#define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) -#define DCU_UPDATE_MODE_MODE (1 << 31) -#define DCU_UPDATE_MODE_READREG (1 << 30) - -#define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16) -#define DCU_CTRLDESCLN_1_WIDTH(x) (x) -#define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16) -#define DCU_CTRLDESCLN_2_POSX(x) (x) -#define DCU_CTRLDESCLN_4_EN (1 << 31) -#define DCU_CTRLDESCLN_4_TILE_EN (1 << 30) -#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29) -#define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28) -#define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20) -#define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16) -#define DCU_CTRLDESCLN_4_RLE_EN (1 << 15) -#define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4) -#define DCU_CTRLDESCLN_4_BB_ON (1 << 2) -#define DCU_CTRLDESCLN_4_AB(x) (x) -#define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16) -#define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8) -#define DCU_CTRLDESCLN_5_CKMAX_B(x) (x) -#define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16) -#define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8) -#define DCU_CTRLDESCLN_6_CKMIN_B(x) (x) -#define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16) -#define DCU_CTRLDESCLN_7_TILE_HOR(x) (x) -#define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x) -#define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x) - -#define BPP_16_RGB565 4 -#define BPP_24_RGB888 5 -#define BPP_32_ARGB8888 6 - -DECLARE_GLOBAL_DATA_PTR; - -/* - * This setting is used for the TWR_LCD_RGB card - */ -static struct fb_videomode fsl_dcu_mode_480_272 = { - .name = "480x272-60", - .refresh = 60, - .xres = 480, - .yres = 272, - .pixclock = 91996, - .left_margin = 2, - .right_margin = 2, - .upper_margin = 1, - .lower_margin = 1, - .hsync_len = 41, - .vsync_len = 2, - .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED -}; - -/* - * This setting is used for Siliconimage SiI9022A HDMI - */ -static struct fb_videomode fsl_dcu_cea_mode_640_480 = { - .name = "640x480-60", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 39722, - .left_margin = 48, - .right_margin = 16, - .upper_margin = 33, - .lower_margin = 10, - .hsync_len = 96, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, -}; - -static struct fb_videomode fsl_dcu_mode_640_480 = { - .name = "640x480-60", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 25175, - .left_margin = 40, - .right_margin = 24, - .upper_margin = 32, - .lower_margin = 11, - .hsync_len = 96, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, -}; - -static struct fb_videomode fsl_dcu_mode_800_480 = { - .name = "800x480-60", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 33260, - .left_margin = 216, - .right_margin = 40, - .upper_margin = 35, - .lower_margin = 10, - .hsync_len = 128, - .vsync_len = 2, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, -}; - -static struct fb_videomode fsl_dcu_mode_1024_600 = { - .name = "1024x600-60", - .refresh = 60, - .xres = 1024, - .yres = 600, - .pixclock = 48000, - .left_margin = 104, - .right_margin = 43, - .upper_margin = 24, - .lower_margin = 20, - .hsync_len = 5, - .vsync_len = 5, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, -}; - -/* - * DCU register map - */ -struct dcu_reg { - u32 desc_cursor[4]; - u32 mode; - u32 bgnd; - u32 disp_size; - u32 hsyn_para; - u32 vsyn_para; - u32 synpol; - u32 threshold; - u32 int_status; - u32 int_mask; - u32 colbar[8]; - u32 div_ratio; - u32 sign_calc[2]; - u32 crc_val; - u8 res_064[0x6c-0x64]; - u32 parr_err_status1; - u8 res_070[0x7c-0x70]; - u32 parr_err_status3; - u32 mparr_err_status1; - u8 res_084[0x90-0x84]; - u32 mparr_err_status3; - u32 threshold_inp_buf[2]; - u8 res_09c[0xa0-0x9c]; - u32 luma_comp; - u32 chroma_red; - u32 chroma_green; - u32 chroma_blue; - u32 crc_pos; - u32 lyr_intpol_en; - u32 lyr_luma_comp; - u32 lyr_chrm_red; - u32 lyr_chrm_grn; - u32 lyr_chrm_blue; - u8 res_0c4[0xcc-0xc8]; - u32 update_mode; - u32 underrun; - u8 res_0d4[0x100-0xd4]; - u32 gpr; - u32 slr_l[2]; - u32 slr_disp_size; - u32 slr_hvsync_para; - u32 slr_pol; - u32 slr_l_transp[2]; - u8 res_120[0x200-0x120]; - u32 ctrldescl[DCU_LAYER_MAX_NUM][16]; -}; - -static void reset_total_layers(void) -{ - struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; - int i; - - for (i = 0; i < DCU_LAYER_MAX_NUM; i++) { - dcu_write32(®s->ctrldescl[i][0], 0); - dcu_write32(®s->ctrldescl[i][1], 0); - dcu_write32(®s->ctrldescl[i][2], 0); - dcu_write32(®s->ctrldescl[i][3], 0); - dcu_write32(®s->ctrldescl[i][4], 0); - dcu_write32(®s->ctrldescl[i][5], 0); - dcu_write32(®s->ctrldescl[i][6], 0); - dcu_write32(®s->ctrldescl[i][7], 0); - dcu_write32(®s->ctrldescl[i][8], 0); - dcu_write32(®s->ctrldescl[i][9], 0); - dcu_write32(®s->ctrldescl[i][10], 0); - } -} - -static int layer_ctrldesc_init(struct fb_info fbinfo, - int index, u32 pixel_format) -{ - struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; - unsigned int bpp = BPP_24_RGB888; - - dcu_write32(®s->ctrldescl[index][0], - DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) | - DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres)); - - dcu_write32(®s->ctrldescl[index][1], - DCU_CTRLDESCLN_2_POSY(0) | - DCU_CTRLDESCLN_2_POSX(0)); - - dcu_write32(®s->ctrldescl[index][2], - (unsigned int)fbinfo.screen_base); - - switch (pixel_format) { - case 16: - bpp = BPP_16_RGB565; - break; - case 24: - bpp = BPP_24_RGB888; - break; - case 32: - bpp = BPP_32_ARGB8888; - break; - default: - printf("unsupported color depth: %u\n", pixel_format); - } - - dcu_write32(®s->ctrldescl[index][3], - DCU_CTRLDESCLN_4_EN | - DCU_CTRLDESCLN_4_TRANS(0xff) | - DCU_CTRLDESCLN_4_BPP(bpp) | - DCU_CTRLDESCLN_4_AB(0)); - - dcu_write32(®s->ctrldescl[index][4], - DCU_CTRLDESCLN_5_CKMAX_R(0xff) | - DCU_CTRLDESCLN_5_CKMAX_G(0xff) | - DCU_CTRLDESCLN_5_CKMAX_B(0xff)); - dcu_write32(®s->ctrldescl[index][5], - DCU_CTRLDESCLN_6_CKMIN_R(0) | - DCU_CTRLDESCLN_6_CKMIN_G(0) | - DCU_CTRLDESCLN_6_CKMIN_B(0)); - - dcu_write32(®s->ctrldescl[index][6], - DCU_CTRLDESCLN_7_TILE_VER(0) | - DCU_CTRLDESCLN_7_TILE_HOR(0)); - - dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); - dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); - - return 0; -} - -int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres, - unsigned int yres, unsigned int pixel_format) -{ - struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; - unsigned int div, mode; -/* - * When DM_VIDEO is enabled reservation of framebuffer is done - * in advance during bind() call. - */ -#if !CONFIG_IS_ENABLED(DM_VIDEO) - fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres * - (fbinfo->var.bits_per_pixel / 8); - - if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) { - fbinfo->screen_size = 0; - return -ENOMEM; - } - /* Reserve framebuffer at the end of memory */ - gd->fb_base = gd->bd->bi_dram[0].start + - gd->bd->bi_dram[0].size - fbinfo->screen_size; - fbinfo->screen_base = (char *)gd->fb_base; - - memset(fbinfo->screen_base, 0, fbinfo->screen_size); -#endif - - reset_total_layers(); - - dcu_write32(®s->disp_size, - DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) | - DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16)); - - dcu_write32(®s->hsyn_para, - DCU_HSYN_PARA_BP(fbinfo->var.left_margin) | - DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) | - DCU_HSYN_PARA_FP(fbinfo->var.right_margin)); - - dcu_write32(®s->vsyn_para, - DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) | - DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) | - DCU_VSYN_PARA_FP(fbinfo->var.lower_margin)); - - dcu_write32(®s->synpol, - DCU_SYN_POL_INV_PXCK_FALL | - DCU_SYN_POL_NEG_REMAIN | - DCU_SYN_POL_INV_VS_LOW | - DCU_SYN_POL_INV_HS_LOW); - - dcu_write32(®s->bgnd, - DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0)); - - dcu_write32(®s->mode, - DCU_MODE_BLEND_ITER(2) | - DCU_MODE_RASTER_EN); - - dcu_write32(®s->threshold, - DCU_THRESHOLD_LS_BF_VS(0x3) | - DCU_THRESHOLD_OUT_BUF_HIGH(0x78) | - DCU_THRESHOLD_OUT_BUF_LOW(0)); - - mode = dcu_read32(®s->mode); - dcu_write32(®s->mode, mode | DCU_MODE_NORMAL); - - layer_ctrldesc_init(*fbinfo, 0, pixel_format); - - div = dcu_set_pixel_clock(fbinfo->var.pixclock); - dcu_write32(®s->div_ratio, (div - 1)); - - dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); - - return 0; -} - -ulong board_get_usable_ram_top(ulong total_size) -{ - return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB; -} - -int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x, - unsigned int *win_y) -{ - const char *options; - unsigned int depth = 0, freq = 0; - - struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272; - - if (!video_get_video_mode(win_x, win_y, &depth, &freq, - &options)) - return -EINVAL; - - /* Find the monitor port, which is a required option */ - if (!options) - return -EINVAL; - - if (strncmp(options, "monitor=", 8) != 0) - return -EINVAL; - - switch (RESOLUTION(*win_x, *win_y)) { - case RESOLUTION(480, 272): - fsl_dcu_mode_db = &fsl_dcu_mode_480_272; - break; - case RESOLUTION(640, 480): - if (!strncmp(options, "monitor=hdmi", 12)) - fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480; - else - fsl_dcu_mode_db = &fsl_dcu_mode_640_480; - break; - case RESOLUTION(800, 480): - fsl_dcu_mode_db = &fsl_dcu_mode_800_480; - break; - case RESOLUTION(1024, 600): - fsl_dcu_mode_db = &fsl_dcu_mode_1024_600; - break; - default: - printf("unsupported resolution %ux%u\n", - *win_x, *win_y); - } - - fbinfo->var.xres = fsl_dcu_mode_db->xres; - fbinfo->var.yres = fsl_dcu_mode_db->yres; - fbinfo->var.bits_per_pixel = 32; - fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock; - fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin; - fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin; - fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin; - fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin; - fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len; - fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len; - fbinfo->var.sync = fsl_dcu_mode_db->sync; - fbinfo->var.vmode = fsl_dcu_mode_db->vmode; - fbinfo->fix.line_length = fbinfo->var.xres * - fbinfo->var.bits_per_pixel / 8; - - return platform_dcu_init(fbinfo, *win_x, *win_y, - options + 8, fsl_dcu_mode_db); -} - -#ifndef CONFIG_DM_VIDEO -static struct fb_info info; - -#if defined(CONFIG_OF_BOARD_SETUP) -int fsl_dcu_fixedfb_setup(void *blob) -{ - u64 start, size; - int ret; - - start = gd->bd->bi_dram[0].start; - size = gd->bd->bi_dram[0].size - info.screen_size; - - /* - * Align size on section size (1 MiB). - */ - size &= 0xfff00000; - ret = fdt_fixup_memory_banks(blob, &start, &size, 1); - if (ret) { - eprintf("Cannot setup fb: Error reserving memory\n"); - return ret; - } - - return 0; -} -#endif - -void *video_hw_init(void) -{ - static GraphicDevice ctfb; - - if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0) - return NULL; - - ctfb.frameAdrs = (unsigned int)info.screen_base; - ctfb.plnSizeX = ctfb.winSizeX; - ctfb.plnSizeY = ctfb.winSizeY; - - ctfb.gdfBytesPP = 4; - ctfb.gdfIndex = GDF_32BIT_X888RGB; - - ctfb.memSize = info.screen_size; - - return &ctfb; -} - -#else /* ifndef CONFIG_DM_VIDEO */ - -static int fsl_dcu_video_probe(struct udevice *dev) -{ - struct video_uc_plat *plat = dev_get_uclass_plat(dev); - struct video_priv *uc_priv = dev_get_uclass_priv(dev); - struct fb_info fbinfo = { 0 }; - unsigned int win_x; - unsigned int win_y; - u32 fb_start, fb_end; - int ret = 0; - - fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); - fb_end = plat->base + plat->size; - fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); - - fbinfo.screen_base = (char *)fb_start; - fbinfo.screen_size = plat->size; - - ret = fsl_probe_common(&fbinfo, &win_x, &win_y); - if (ret < 0) - return ret; - - uc_priv->bpix = VIDEO_BPP32; - uc_priv->xsize = win_x; - uc_priv->ysize = win_y; - - /* Enable dcache for the frame buffer */ - mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, - DCACHE_WRITEBACK); - video_set_flush_dcache(dev, true); - return ret; -} - -static int fsl_dcu_video_bind(struct udevice *dev) -{ - struct video_uc_plat *plat = dev_get_uclass_plat(dev); - unsigned int win_x; - unsigned int win_y; - unsigned int depth = 0, freq = 0; - const char *options; - int ret = 0; - - ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options); - if (ret < 0) - return ret; - - plat->size = win_x * win_y * 32; - - return 0; -} - -static const struct udevice_id fsl_dcu_video_ids[] = { - { .compatible = "fsl,vf610-dcu" }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(fsl_dcu_video) = { - .name = "fsl_dcu_video", - .id = UCLASS_VIDEO, - .of_match = fsl_dcu_video_ids, - .bind = fsl_dcu_video_bind, - .probe = fsl_dcu_video_probe, - .flags = DM_FLAG_PRE_RELOC, -}; -#endif /* ifndef CONFIG_DM_VIDEO */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 3711e429a70..2e7b640357e 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -14,13 +14,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#ifdef CONFIG_VIDEO_FSL_DCU_FB -#define CONFIG_SYS_FSL_DCU_LE - -#define CONFIG_SYS_DCU_ADDR DCU0_BASE_ADDR -#define DCU_LAYER_MAX_NUM 64 -#endif - /* NAND support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 54860af946b..94749c1f7f1 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -303,16 +303,6 @@ * MMC */
-/* - * Video - */ -#ifdef CONFIG_VIDEO_FSL_DCU_FB -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 -#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 -#endif - /* * eTSEC */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index dd47ba5efc6..7292ee8e836 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -190,19 +190,6 @@ #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 1
-/* - * MMC - */ - -/* - * Video - */ -#ifdef CONFIG_VIDEO_FSL_DCU_FB -#define CONFIG_FSL_DCU_SII9022A -#define CONFIG_SYS_I2C_DVI_BUS_NUM 1 -#define CONFIG_SYS_I2C_DVI_ADDR 0x39 -#endif - /* * eTSEC */ diff --git a/include/fsl_dcu_fb.h b/include/fsl_dcu_fb.h deleted file mode 100644 index 7a5347a9247..00000000000 --- a/include/fsl_dcu_fb.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * FSL DCU Framebuffer driver - */ -#include <linux/fb.h> - -int fsl_dcu_init(struct fb_info *fbinfo, - unsigned int xres, - unsigned int yres, - unsigned int pixel_format); - -int fsl_dcu_fixedfb_setup(void *blob); - -/* Prototypes for external board-specific functions */ -int platform_dcu_init(struct fb_info *fbinfo, - unsigned int xres, - unsigned int yres, - const char *port, - struct fb_videomode *dcu_fb_videomode); -unsigned int dcu_set_pixel_clock(unsigned int pixclock); diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 536a8ee13f6..f63eddfea4f 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -210,7 +210,6 @@ CONFIG_FPGA_STRATIX_V CONFIG_FSL_CADMUS CONFIG_FSL_CORENET CONFIG_FSL_CPLD -CONFIG_FSL_DCU_SII9022A CONFIG_FSL_DEVICE_DISABLE CONFIG_FSL_DIU_CH7301 CONFIG_FSL_DIU_FB @@ -1218,8 +1217,6 @@ CONFIG_SYS_FSL_DCSR_DDR2_ADDR CONFIG_SYS_FSL_DCSR_DDR3_ADDR CONFIG_SYS_FSL_DCSR_DDR4_ADDR CONFIG_SYS_FSL_DCSR_DDR_ADDR -CONFIG_SYS_FSL_DCU_BE -CONFIG_SYS_FSL_DCU_LE CONFIG_SYS_FSL_DDR2_ADDR CONFIG_SYS_FSL_DDR3_ADDR CONFIG_SYS_FSL_DDR_ADDR