On Tue, May 07, 2013 at 04:30:50PM +0800, Liu Gang wrote:
When a T4 board boots from SRIO or PCIE, it needs to finish these processes:
- Set all the cores in holdoff status.
- Set the boot location to one PCIE or SRIO interface by RCW.
- Set a specific TLB entry for the boot process.
- Set a LAW entry with the TargetID of one PCIE or SRIO for the boot.
- Set a specific TLB entry in order to fetch ucode and ENV from master.
- Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV.
- Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet.
Signed-off-by: Liu Gang Gang.Liu@freescale.com
Applied with fixes for build errors. I think this was just an issue of this patch arriving before the T4 consolidation patch, but please be careful.
diff --git a/boards.cfg b/boards.cfg index 61acc3f..354738e 100644 --- a/boards.cfg +++ b/boards.cfg @@ -896,6 +896,7 @@ stxssa_4M powerpc mpc85xx stxssa stx T4240QDS powerpc mpc85xx t4qds freescale T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +T4240QDS_SRIO_PCIE_BOOT powerpc mpc85xx t4qds freescale - T4240QDS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
Had to fix this line so it included PPC_T4240, for future reference
Thanks, Andy