Add npcm8xx A2 cpu version check and add 4G RAM support
Signed-off-by: Jim Liu JJLIU0@nuvoton.com --- arch/arm/include/asm/arch-npcm8xx/gcr.h | 1 + arch/arm/mach-npcm/npcm8xx/cpu.c | 12 ++++- board/nuvoton/arbel_evb/arbel_evb.c | 70 +++++++++++++++++++++++-- 3 files changed, 79 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-npcm8xx/gcr.h b/arch/arm/include/asm/arch-npcm8xx/gcr.h index ee6677a0e5..20230d64e6 100644 --- a/arch/arm/include/asm/arch-npcm8xx/gcr.h +++ b/arch/arm/include/asm/arch-npcm8xx/gcr.h @@ -12,6 +12,7 @@ /* On-Chip ARBEL NPCM8XX VERSIONS */ #define ARBEL_Z1 0x00A35850 #define ARBEL_A1 0x04a35850 +#define ARBEL_A2 0x08a35850 #define ARBEL_NPCM845 0x00000000 #define ARBEL_NPCM830 0x00300395 #define ARBEL_NPCM810 0x00000220 diff --git a/arch/arm/mach-npcm/npcm8xx/cpu.c b/arch/arm/mach-npcm/npcm8xx/cpu.c index 2d839cfae9..af59452609 100644 --- a/arch/arm/mach-npcm/npcm8xx/cpu.c +++ b/arch/arm/mach-npcm/npcm8xx/cpu.c @@ -68,6 +68,9 @@ int print_cpuinfo(void) case ARBEL_A1: printf("A1 @ "); break; + case ARBEL_A2: + printf("A2 @ "); + break; default: printf("Unknown\n"); break; @@ -92,7 +95,7 @@ int arch_cpu_init(void) return 0; }
-static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = { +static struct mm_region npcm_mem_map[] = { { /* DRAM */ .phys = 0x0UL, @@ -109,6 +112,13 @@ static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + { + .phys = 0x100000000UL, + .virt = 0x100000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { /* List terminator */ 0, diff --git a/board/nuvoton/arbel_evb/arbel_evb.c b/board/nuvoton/arbel_evb/arbel_evb.c index cd12ce3834..e52e0a59ab 100644 --- a/board/nuvoton/arbel_evb/arbel_evb.c +++ b/board/nuvoton/arbel_evb/arbel_evb.c @@ -8,6 +8,17 @@ #include <asm/io.h> #include <asm/arch/gcr.h>
+#define SR_MII_CTRL_SWR_BIT15 15 + +#define DRAM_512MB_ECC_SIZE 0x1C000000ULL +#define DRAM_512MB_SIZE 0x20000000ULL +#define DRAM_1GB_ECC_SIZE 0x38000000ULL +#define DRAM_1GB_SIZE 0x40000000ULL +#define DRAM_2GB_ECC_SIZE 0x70000000ULL +#define DRAM_2GB_SIZE 0x80000000ULL +#define DRAM_4GB_ECC_SIZE 0xE00000000ULL +#define DRAM_4GB_SIZE 0x100000000ULL + DECLARE_GLOBAL_DATA_PTR;
int board_init(void) @@ -18,12 +29,65 @@ int board_init(void) int dram_init(void) { struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA; + uint64_t delta = 0ULL;
/* - * Get dram size from bootblock. - * The value is stored in scrpad_02 register. + * get dram active size value from bootblock. + * Value sent using scrpad_03 register. + * feature available in bootblock 0.0.6 and above. */ - gd->ram_size = readl(&gcr->scrpad_b); + + gd->ram_size = readl(&gcr->scrpad_c); + debug("%s: scrpad_c: %llx ", __func__, gd->ram_size); + + if (gd->ram_size == 0) { + gd->ram_size = readl(&gcr->scrpad_b); + debug("%s: scrpad_b: %llx ", __func__, gd->ram_size); + } else { + gd->ram_size *= 0x100000ULL; + } + + gd->bd->bi_dram[0].start = 0; + debug("ram_size: %llx ", gd->ram_size); + + switch (gd->ram_size) { + case DRAM_512MB_ECC_SIZE: + case DRAM_512MB_SIZE: + case DRAM_1GB_ECC_SIZE: + case DRAM_1GB_SIZE: + case DRAM_2GB_ECC_SIZE: + case DRAM_2GB_SIZE: + gd->bd->bi_dram[0].size = gd->ram_size; + gd->bd->bi_dram[1].start = 0; + gd->bd->bi_dram[1].size = 0; + break; + case DRAM_4GB_ECC_SIZE: + gd->bd->bi_dram[0].size = DRAM_2GB_ECC_SIZE; + gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; + gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; + delta = DRAM_4GB_SIZE - DRAM_2GB_ECC_SIZE; + break; + case DRAM_4GB_SIZE: + gd->bd->bi_dram[0].size = DRAM_2GB_SIZE; + gd->bd->bi_dram[1].start = DRAM_4GB_SIZE; + gd->bd->bi_dram[1].size = DRAM_2GB_SIZE; + delta = DRAM_4GB_SIZE - DRAM_2GB_SIZE; + break; + default: + gd->bd->bi_dram[0].size = DRAM_1GB_SIZE; + gd->bd->bi_dram[1].start = 0; + gd->bd->bi_dram[1].size = 0; + break; + } + + gd->ram_size -= delta; + + return 0; +} + +int dram_init_banksize(void) +{ + dram_init();
return 0; }