diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile
index 8d4e478..c446202 100644
--- a/cpu/arm920t/at91rm9200/Makefile
+++ b/cpu/arm920t/at91rm9200/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).a
 
 COBJS	= bcm5221.o dm9161.o ether.o i2c.o interrupts.o \
-	  lxt972.o serial.o usb_ohci.o
+	  lxt972.o nand.o serial.o usb_ohci.o
 SOBJS	= lowlevel_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/arm920t/at91rm9200/nand.c b/cpu/arm920t/at91rm9200/nand.c
new file mode 100644
index 0000000..a66c593
--- /dev/null
+++ b/cpu/arm920t/at91rm9200/nand.c
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NAND)
+
+#include <nand.h>
+#include <asm/arch/AT91RM9200.h>
+
+/*
+ * Hardware specific access to control-lines.  CLE and ALE signals
+ * are manipulated by simply setting/clearing address bits.
+ */
+static void at91_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+{
+	struct nand_chip *nand_chip = mtd->priv;
+
+	switch(cmd) {
+		case NAND_CTL_SETCLE:
+ 			nand_chip->IO_ADDR_W =
+				(void *)(CFG_NAND_BASE + (1 << CFG_NAND_AT91_CLE_BIT));
+			break;
+		case NAND_CTL_CLRCLE:
+			nand_chip->IO_ADDR_W = (void *) CFG_NAND_BASE;
+			break;
+		case NAND_CTL_SETALE:
+			nand_chip->IO_ADDR_W =
+				(void *)(CFG_NAND_BASE + (1 << CFG_NAND_AT91_ALE_BIT));
+			break;
+		case NAND_CTL_CLRALE:
+			nand_chip->IO_ADDR_W = (void *) CFG_NAND_BASE;
+			break;
+		case NAND_CTL_SETNCE:
+			*AT91C_PIOC_CODR = AT91C_PC0_BFCK;
+			break;
+		case NAND_CTL_CLRNCE:
+			*AT91C_PIOC_SODR = AT91C_PC0_BFCK;
+			break;
+	}
+}
+
+/*
+ * Read the Device Ready pin.
+ */
+static int at91_nand_device_ready(struct mtd_info *mtd)
+{
+	unsigned pioc_pdsr = *AT91C_PIOC_PDSR;
+
+	return (pioc_pdsr & AT91C_PC2_BFAVD) != 0;
+}
+
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for  accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
+ *   only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ *   read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ *   nand_scan about special functionality. See the defines for further
+ *   explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+void board_nand_init(struct nand_chip *nand)
+{
+
+	/* Setup Smart Media, fitst enable the address range of CS3 */
+	*AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia;
+
+	/* set the bus interface characteristics based on
+	   tDS Data Set up Time 30 - ns
+	   tDH Data Hold Time 20 - ns
+	   tALS ALE Set up Time 20 - ns
+	   16ns at 60 MHz ~= 3  */
+
+	#define SM_ID_RWH	(5 << 28)
+	#define SM_RWH		(1 << 28)
+	#define SM_RWS		(0 << 24)
+	#define SM_TDF		(1 << 8)
+	#define SM_NWS		(5)
+
+	AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS |
+		AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 |
+		SM_TDF | AT91C_SMC2_WSEN | SM_NWS);
+
+	/* enable SMOE and SMWE */
+	*AT91C_PIOC_ASR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
+	*AT91C_PIOC_PDR = AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE;
+
+	/* Configure PC0 as SMCE output, and set to 1 (low?) */
+	*AT91C_PIOC_SODR = AT91C_PC0_BFCK;
+	*AT91C_PIOC_PER = AT91C_PC0_BFCK;
+	*AT91C_PIOC_OER = AT91C_PC0_BFCK;
+
+	/* Configure PC2 as SMRB input (signal READY of the SmartMedia) */
+	*AT91C_PIOC_PER = AT91C_PC2_BFAVD;	/* enable direct output enable */
+	*AT91C_PIOC_ODR = AT91C_PC2_BFAVD;	/* disable output */
+
+	/* PIOC clock enabling */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_PIOC;
+
+	/* Set the chip-specific options */
+	nand->hwcontrol = at91_nand_hwcontrol;
+	nand->dev_ready = at91_nand_device_ready;
+	nand->eccmode = NAND_ECC_SOFT;
+	nand->chip_delay = CFG_NAND_CHIP_DELAY;
+}
+#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 97d4704..3cd5601 100644
--- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -754,6 +754,7 @@ #define AT91C_TCB0_BMR		((AT91_REG *)	0x
 #define AT91C_TCB0_BCR		((AT91_REG *)	0xFFFA00C0) /* (TCB0) TC Block Control Register */
 #define AT91C_PIOC_PDR		((AT91_REG *)	0xFFFFF804) /* (PIOC) PIO Disable Register */
 #define AT91C_PIOC_PER		((AT91_REG *)	0xFFFFF800) /* (PIOC) PIO Enable Register */
+#define AT91C_PIOC_OER  	((AT91_REG *)	0xFFFFF810) /* (PIOC) Output Enable Registerr */
 #define AT91C_PIOC_ODR  	((AT91_REG *)	0xFFFFF814) /* (PIOC) Output Disable Registerr */
 #define AT91C_PIOB_PER		((AT91_REG *)	0xFFFFF600) /* (PIOB) PIO Enable Register */
 #define AT91C_PIOB_ODR		((AT91_REG *)	0xFFFFF614) /* (PIOB) Output Disable Registerr */
