[U-Boot] [PATCH V3] ppc4xx: Remove CANBT board

7 Aug 2013

This board and especially the CPU (PPC405CR) is EOL.
Signed-off-by: Matthias Fuchs matthias.fuchs@esd.eu
---
V2: add entry to doc/README.scrapyard
V3: add missing commit IDs in README.scrapyard
MAINTAINERS                |    1 -
 board/esd/canbt/Makefile   |   31 --
 board/esd/canbt/canbt.c    |  164 ---------
 board/esd/canbt/canbt.h    |   28 --
 board/esd/canbt/flash.c    |   68 ----
 board/esd/canbt/fpgadata.c |  807 --------------------------------------------
 boards.cfg                 |    1 -
 doc/README.scrapyard       |    7 +-
 include/configs/CANBT.h    |  215 ------------
 9 files changed, 4 insertions(+), 1318 deletions(-)
 delete mode 100644 board/esd/canbt/Makefile
 delete mode 100644 board/esd/canbt/canbt.c
 delete mode 100644 board/esd/canbt/canbt.h
 delete mode 100644 board/esd/canbt/flash.c
 delete mode 100644 board/esd/canbt/fpgadata.c
 delete mode 100644 include/configs/CANBT.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 081cf96..bc4b867 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -184,7 +184,6 @@ Matthias Fuchs matthias.fuchs@esd-electronics.com
    APC405		PPC405GP
    AR405		PPC405GP
    ASH405		PPC405EP
-	CANBT		PPC405CR
    CPCI2DP		PPC405GP
    CPCI405		PPC405GP
    CPCI4052	PPC405GP
diff --git a/board/esd/canbt/Makefile b/board/esd/canbt/Makefile
deleted file mode 100644
index e5caf23..0000000
--- a/board/esd/canbt/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o ../common/misc.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c
deleted file mode 100644
index 5884975..0000000
--- a/board/esd/canbt/canbt.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * (C) Copyright 2001
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include "canbt.h"
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* fpga configuration data */
-const unsigned char fpgadata[] = {
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-int board_early_init_f (void)
-{
-	unsigned long CPC0_CR0Reg;
-	int index, len, i;
-	int status;
-
-	/*
-	 * Setup GPIO pins
-	 */
-	CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff;
-	CPC0_CR0Reg |= 0x0070f000;
-	mtdcr (CPC0_CR0, CPC0_CR0Reg);
-
-#ifdef FPGA_DEBUG
-	/* set up serial port with default baudrate */
-	(void) get_clocks ();
-	gd->baudrate = CONFIG_BAUDRATE;
-	serial_init ();
-	console_init_f ();
-#endif
-
-	/*
-	 * Boot onboard FPGA
-	 */
-	status = fpga_boot ((unsigned char *) fpgadata, sizeof (fpgadata));
-	if (status != 0) {
-		/* booting FPGA failed */
-#ifndef FPGA_DEBUG
-		/* set up serial port with default baudrate */
-		(void) get_clocks ();
-		gd->baudrate = CONFIG_BAUDRATE;
-		serial_init ();
-		console_init_f ();
-#endif
-		printf ("\nFPGA: Booting failed ");
-		switch (status) {
-		case ERROR_FPGA_PRG_INIT_LOW:
-			printf ("(Timeout: INIT not low after asserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_INIT_HIGH:
-			printf ("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_DONE:
-			printf ("(Timeout: DONE not high after programming FPGA)\n ");
-			break;
-		}
-
-		/* display infos on fpgaimage */
-		index = 15;
-		for (i = 0; i < 4; i++) {
-			len = fpgadata[index];
-			printf ("FPGA: %s\n", &(fpgadata[index + 1]));
-			index += len + 3;
-		}
-		putc ('\n');
-		/* delayed reboot */
-		for (i = 20; i > 0; i--) {
-			printf ("Rebooting in %2d seconds \r", i);
-			for (index = 0; index < 1000; index++)
-				udelay (1000);
-		}
-		putc ('\n');
-		do_reset (NULL, 0, 0, NULL);
-	}
-
-	/*
-	 * Setup port pins for normal operation
-	 */
-	out_be32 ((void *)GPIO0_ODR, 0x00000000);	/* no open drain pins */
-	out_be32 ((void *)GPIO0_TCR, 0x07038100);	/* setup for output */
-	out_be32 ((void *)GPIO0_OR, 0x07030100);	/* set output pins to high (default) */
-
-	/*
-	 * IRQ 0-15  405GP internally generated; active high; level sensitive
-	 * IRQ 16    405GP internally generated; active low; level sensitive
-	 * IRQ 17-24 RESERVED
-	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
-	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
-	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
-	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
-	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
-	 */
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
-	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
-	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	int index;
-	int len;
-	char str[64];
-	int i = getenv_f("serial#", str, sizeof (str));
-
-	puts ("Board: ");
-
-	if (!i || strncmp (str, "CANBT", 5)) {
-		puts ("### No HW ID - assuming CANBT\n");
-		return (0);
-	}
-
-	puts (str);
-
-	puts ("\nFPGA:  ");
-
-	/* display infos on fpgaimage */
-	index = 15;
-	for (i = 0; i < 4; i++) {
-		len = fpgadata[index];
-		printf ("%s ", &(fpgadata[index + 1]));
-		index += len + 3;
-	}
-
-	putc ('\n');
-
-	return 0;
-}
diff --git a/board/esd/canbt/canbt.h b/board/esd/canbt/canbt.h
deleted file mode 100644
index 75e7950..0000000
--- a/board/esd/canbt/canbt.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- *                          Start Address    Length
- * +-----------------------+ 0x4000_0000     Start of Flash -----------------
- * | MON8xx code           | 0x4000_0100     Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused)              |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses    |                 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) |                 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address          |                 0x04
- * +-----------------------+ 0x4001_FFC0                     ^
- * | Hardware Information  |                 0x40            | MON8xx
- * +=======================+ 0x4002_0000 (sector border)    -----------------
- * | Autostart Header      |                                 | Applications
- * | ...                   |                                 v
- *
- *****************************************************************************/
diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c
deleted file mode 100644
index 34bdc05..0000000
--- a/board/esd/canbt/flash.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	unsigned long size_b0;
-	int i;
-	uint pbcr;
-	unsigned long base_b0;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	/* Setup offsets */
-	flash_get_offsets (-size_b0, &flash_info[0]);
-
-	/* Re-do sizing to get full correct info */
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	pbcr = mfdcr(EBC0_CFGDATA);
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	base_b0 = -size_b0;
-	pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
-	mtdcr(EBC0_CFGDATA, pbcr);
-	/*          printf("PB1CR = %x\n", pbcr); */
-
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -monitor_flash_len,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	flash_info[0].size = size_b0;
-
-	return (size_b0);
-}
diff --git a/board/esd/canbt/fpgadata.c b/board/esd/canbt/fpgadata.c
deleted file mode 100644
index af401cd..0000000
--- a/board/esd/canbt/fpgadata.c
+++ /dev/null
@@ -1,807 +0,0 @@
-0x00, 0x09, 0x0f, 0xf0, 0x0f, 0xf0, 0x0f, 0xf0,
-0x0f, 0xf0, 0x00, 0x00, 0x01, 0x61, 0x00, 0x0c,
-0x69, 0x6f, 0x5f, 0x63, 0x68, 0x69, 0x70, 0x2e,
-0x6e, 0x63, 0x64, 0x00, 0x62, 0x00, 0x0b, 0x73,
-0x30, 0x35, 0x78, 0x6c, 0x76, 0x71, 0x31, 0x30,
-0x30, 0x00, 0x63, 0x00, 0x0b, 0x32, 0x30, 0x30,
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-0x3a, 0x34, 0x33, 0x00, 0x65, 0xe2, 0x01, 0x00,
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-0x79, 0xe5, 0x01, 0x0e, 0x09, 0x09, 0x09, 0x09,
-0x08, 0x02, 0x09, 0x09, 0x09, 0x09, 0x11, 0xe6,
-0x3e, 0x3b, 0x02, 0x10, 0x09, 0x09, 0x09, 0x09,
-0x0b, 0x09, 0x09, 0x09, 0x09, 0x10, 0xe5, 0x7d,
-0x3f, 0x3a, 0xe5, 0x01, 0x3f, 0x36, 0x04, 0x02,
-0x7a, 0x01, 0x01, 0x13, 0x3d, 0x28, 0x01, 0x01,
-0x3f, 0x33, 0x0a, 0x3f, 0x34, 0x08, 0xe5, 0x79,
-0x01, 0x01, 0x14, 0x09, 0x09, 0x09, 0x09, 0x0b,
-0x09, 0x09, 0x09, 0x09, 0x09, 0xe5, 0x01, 0x0f,
-0x09, 0x09, 0x09, 0x09, 0x07, 0x03, 0x09, 0x09,
-0x09, 0x08, 0xe5, 0x0d, 0x03, 0x3a, 0x04, 0x3a,
-0x02, 0xe5, 0x0c, 0x09, 0x03, 0x05, 0x09, 0x09,
-0x03, 0x07, 0x09, 0x09, 0x07, 0x01, 0x1b, 0x01,
-0xe5, 0x0a, 0x02, 0x07, 0x05, 0x03, 0x01, 0x03,
-0x03, 0x01, 0x03, 0x03, 0x09, 0x06, 0xe5, 0x02,
-0x04, 0x04, 0x04, 0x02, 0x06, 0xe5, 0x02, 0x02,
-0x06, 0x02, 0xe5, 0x02, 0x03, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-0xff,
diff --git a/boards.cfg b/boards.cfg
index 944ed4c..babf7dc 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -1108,7 +1108,6 @@ PPChameleonEVB_ME_33         powerpc     ppc4xx      PPChameleonEVB      dave
 APC405                       powerpc     ppc4xx      apc405              esd
 AR405                        powerpc     ppc4xx      ar405               esd
 ASH405                       powerpc     ppc4xx      ash405              esd
-CANBT                        powerpc     ppc4xx      canbt               esd
 CMS700                       powerpc     ppc4xx      cms700              esd
 CPCI2DP                      powerpc     ppc4xx      cpci2dp             esd
 CPCI405                      powerpc     ppc4xx      cpci405             esd
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index a0f1fa3..87b1dfe 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,9 +11,10 @@ easily if here is something they might want to dig for...
Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
-Alaska8220       powerpc     mpc8220        -           -
-Yukon8220        powerpc     mpc8220        -           -
-sorcery          powerpc     mpc8220        -           -
+CANBT            powerpc     405CR          -           -           Matthias Fuchs matthias.fuchs@esd.eu
+Alaska8220       powerpc     mpc8220        d6ed322     2013-05-11
+Yukon8220        powerpc     mpc8220        d6ed322     2013-05-11
+sorcery          powerpc     mpc8220        d6ed322     2013-05-11
 smdk6400         arm         arm1176        52587f1	2013-04-12  Zhong Hongbo bocui107@gmail.com
 ns9750dev        arm         arm926ejs      4cfc611	2013-02-28  Markus Pietrek mpietrek@fsforth.de
 AMX860           powerpc     mpc860         1b0757e     2012-10-28  Wolfgang Denk wd@denx.de
diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h
deleted file mode 100644
index 40471b7..0000000
--- a/include/configs/CANBT.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * (C) Copyright 2001
- * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+ 
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405CR		1	/* This is a PPC405CR CPU	*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_CANBT		1	/* ...on a CANBT board		*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	1	/* autoboot after 1 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw console=ttyS0,115200; "	\
-	"bootm ffe00000 ffe80000"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
-
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_EEPROM
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#define CONFIG_SYS_EXT_SERIAL_CLOCK	14745600 /* use external serial clock	*/
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(~(CONFIG_SYS_TEXT_BASE) + 1)
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use FLASH for environment variables */
-
-#define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_OFFSET		0x00010000	/* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
-
-#define CONFIG_ENV_SECT_SIZE	0x10000 /* see README - env sector total size	*/
-
-#else /* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x400	/* 1024 bytes may be used for env vars */
-				   /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address	*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (CAN/USB) initialization					*/
-#define CONFIG_SYS_EBC_PB1AP		0x010053C0  /* enable Ready, BEM=1		*/
-#define CONFIG_SYS_EBC_PB1CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (Misc-IO/LEDs) initialization					*/
-#define CONFIG_SYS_EBC_PB2AP		0x000004c0  /* no Ready, BEM=1			*/
-#define CONFIG_SYS_EBC_PB2CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (CAN Features) initialization					*/
-#define CONFIG_SYS_EBC_PB3AP		0x80000040  /* no Ready, BEM=1			*/
-#define CONFIG_SYS_EBC_PB3CR		0xF021C000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in RAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x00ef0000 /* inside of SDRAM			*/
-#define CONFIG_SYS_INIT_RAM_SIZE	0x0f00	/* Size of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif	/* __CONFIG_H */
-- 
1.7.9.5


    