Since the hardware can handle it, bump the default clocks from 80mhz SCLK and 398mhz CCLK to 100mhz SCLK and 498mhz CCLK.
Signed-off-by: Mike Frysinger vapier@gentoo.org --- include/configs/bf533-stamp.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index ea5cf41..b1cdf49 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -30,7 +30,7 @@ #define CONFIG_PLL_BYPASS 0 /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ /* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 36 +#define CONFIG_VCO_MULT 45 /* CCLK_DIV controls the core clock divider */ /* Values can be 1, 2, 4, or 8 ONLY */ #define CONFIG_CCLK_DIV 1