Re: [U-Boot] [PATCH 2/3] armv8/fsl_lsch2: Add LS1046A SoC support

-----Original Message----- From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Gong Qianyu Sent: Thursday, June 30, 2016 3:31 PM To: york sun york.sun@nxp.com; u-boot@lists.denx.de Cc: Mihai Bantea mihai.bantea@freescale.com; Zhiqiang Hou zhiqiang.hou@nxp.com; Wenbin Song wenbin.song@nxp.com; Mingkai Hu mingkai.hu@nxp.com Subject: [U-Boot] [PATCH 2/3] armv8/fsl_lsch2: Add LS1046A SoC support

From: Mingkai Hu mingkai.hu@nxp.com

The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support.

Please add SoC details in arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Signed-off-by: Mihai Bantea mihai.bantea@freescale.com Signed-off-by: Mingkai Hu mingkai.hu@nxp.com Signed-off-by: Gong Qianyu Qianyu.Gong@nxp.com

Strange missing list of file modified :)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index eb2cbc3..4df467d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -32,3 +32,7 @@ endif ifneq ($(CONFIG_LS1012A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o endif

+ifneq ($(CONFIG_LS1046A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index fe3444a..f73092a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -13,6 +13,9 @@ #ifdef CONFIG_SYS_FSL_SRDS_1 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; #endif +#ifdef CONFIG_SYS_FSL_SRDS_2 +static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; +#endif

int is_serdes_configured(enum srds_prtcl device) { @@ -21,6 +24,9 @@ int is_serdes_configured(enum srds_prtcl device) #ifdef CONFIG_SYS_FSL_SRDS_1 ret |= serdes1_prtcl_map[device]; #endif +#ifdef CONFIG_SYS_FSL_SRDS_2

• ret |= serdes2_prtcl_map[device];

+#endif

return !!ret; } @@ -38,6 +44,12 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; break; #endif +#ifdef CONFIG_SYS_FSL_SRDS_2

• case FSL_SRDS_2:

• cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
  

• cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
  

• break;
  

+#endif default: printf("invalid SerDes%d\n", sd); break; @@ -114,4 +126,11 @@ void fsl_serdes_init(void) FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT, serdes1_prtcl_map); #endif +#ifdef CONFIG_SYS_FSL_SRDS_2

• serdes_init(FSL_SRDS_2,

•     CONFIG_SYS_FSL_SERDES_ADDR,
  

•     FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
  

•     FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
  

•     serdes2_prtcl_map);
  

+#endif }

Ideally this should be separate patch. Like Adding support of SerDes2

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index d0dc58d..8922197 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info) case 3: sys_info->freq_fman[0] = freq_c_pll[0] / 3; break;

• case 4:

• sys_info->freq_fman[0] = freq_c_pll[0] / 4;
  

• break;
  

• case 5:

• sys_info->freq_fman[0] = sys_info->freq_systembus;
  

• break;
  

  case 6: sys_info->freq_fman[0] = freq_c_pll[1] / 2; break;

@@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info) #ifdef CONFIG_FSL_ESDHC #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK rcw_tmp = in_be32(&gur->rcwsr[15]);

• rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >>

HWA_CGA_M2_CLK_SHIFT;

• sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;

• switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >>

HWA_CGA_M2_CLK_SHIFT) {

• case 1:

• sys_info->freq_sdhc = freq_c_pll[1];
  

• break;
  

• case 2:

• sys_info->freq_sdhc = freq_c_pll[1] / 2;
  

• break;
  

• case 3:

• sys_info->freq_sdhc = freq_c_pll[1] / 3;
  

• break;
  

• case 6:

• sys_info->freq_sdhc = freq_c_pll[0] / 2;
  

• break;
  

• default:

• printf("Error: Unknown ESDHC clock select!\n");
  

• break;
  

• }

#else sys_info->freq_sdhc = sys_info->freq_systembus; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c new file mode 100644 index 0000000..1da6b71 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -0,0 +1,99 @@ +/*

• • Copyright 2016 Freescale Semiconductor, Inc.
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/immap_lsch2.h>

+struct serdes_config {

• u32 protocol;
• u8 lanes[SRDS_MAX_LANES];

+};

+static struct serdes_config serdes1_cfg_tbl[] = {

• /* SerDes 1 */
• {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,

SGMII_FM1_DTSEC5,

•   SGMII_FM1_DTSEC6} },
  

• {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5,

•   SGMII_FM1_DTSEC6} },
  

• {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10,

SGMII_FM1_DTSEC5,

•   SGMII_FM1_DTSEC6} },
  

• {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10,

SGMII_FM1_DTSEC5,

•   SGMII_FM1_DTSEC6} },
  

• {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,

•   SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  

• {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} },
• {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE}

},

• {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1,

SGMII_FM1_DTSEC6} },

• {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,

PCIE1,

•   SGMII_FM1_DTSEC6} },
  

• {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1,

•   SGMII_FM1_DTSEC6} },
  

• {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,

•   SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
  

• {}

+};

+static struct serdes_config serdes2_cfg_tbl[] = {

• /* SerDes 2 */
• {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} },
• {0x5559, {PCIE1, PCIE2, PCIE3, SATA1} },
• {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} },
• {0x5506, {PCIE1, PCIE2, NONE, PCIE3} },
• {0x0506, {NONE, PCIE2, NONE, PCIE3} },
• {0x0559, {NONE, PCIE2, PCIE3, SATA1} },
• {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} },
• {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} },
• {}

+};

+static struct serdes_config *serdes_cfg_tbl[] = {

• serdes1_cfg_tbl,
• serdes2_cfg_tbl,

+};

+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) {

• struct serdes_config *ptr;
• if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))

• return 0;
  

• ptr = serdes_cfg_tbl[serdes];
• while (ptr->protocol) {

• if (ptr->protocol == cfg)
  

• 	return ptr->lanes[lane];
  

• ptr++;
  

• }
• return 0;

+}

+int is_serdes_prtcl_valid(int serdes, u32 prtcl) {

• int i;
• struct serdes_config *ptr;
• if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))

• return 0;
  

• ptr = serdes_cfg_tbl[serdes];
• while (ptr->protocol) {

• if (ptr->protocol == prtcl)
  

• 	break;
  

• ptr++;
  

• }
• if (!ptr->protocol)

• return 0;
  

• for (i = 0; i < SRDS_MAX_LANES; i++) {

• if (ptr->lanes[i] != NONE)
  

• 	return 1;
  

• }
• return 0;

+} diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 44fe0c0..85e21fc 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -229,6 +229,52 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_SEC_BE +#elif defined(CONFIG_LS1046A) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4

Does LS1046 support IFC?

+#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 +#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ +#define CONFIG_SYS_FSL_DDR_BE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE

+#define CONFIG_SYS_FSL_CCSR_GUR_BE +#define CONFIG_SYS_FSL_CCSR_SCFG_BE +#define CONFIG_SYS_FSL_IFC_BE

Does LS1046 support IFC?

+#define CONFIG_SYS_FSL_ESDHC_BE +#define CONFIG_SYS_FSL_WDOG_BE +#define CONFIG_SYS_FSL_DSPI_BE +#define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_PEX_LUT_BE

+#define SRDS_MAX_LANES 4 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SRDS_2

+#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SNVS_LE +#define CONFIG_SYS_FSL_SEC_BE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE +#define CONFIG_KEY_REVOCATION

+/* SMMU Defintions */ +#define SMMU_BASE 0x09000000

+/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x01410000 +#define GICC_BASE 0x01420000

+#define CONFIG_SYS_FSL_ERRATUM_A009929

Is this errata confirmed for this SoC?

+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 197b0eb..b9a3c19 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -13,6 +13,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),

• CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),

If possible, please add other personality also.

CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 487cba8..bd8494a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -140,6 +140,7 @@ enum srds_prtcl {

enum srds { FSL_SRDS_1 = 0,

• FSL_SRDS_2 = 1,

};

#endif @@ -150,7 +151,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device); enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); int is_serdes_prtcl_valid(int serdes, u32 prtcl);

-#ifdef CONFIG_LS1043A +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)

Please try to use chassis specific define

const char *serdes_clock_to_string(u32 clock); int get_serdes_protocol(void); #endif diff --git a/arch/arm/include/asm/arch- fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl- layerscape/immap_lsch2.h index cbb252c..05f497c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -228,6 +228,8 @@ struct ccsr_gur { #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff +#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 #define RCW_SB_EN_REG_INDEX 7 #define RCW_SB_EN_MASK 0x00200000

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 39e8c7a..5ea6205 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -44,6 +44,7 @@ struct cpu_type { #define SVR_LS1012A 0x870400 #define SVR_LS1043A 0x879200 #define SVR_LS1023A 0x879208 +#define SVR_LS1046A 0x870704 #define SVR_LS2045A 0x870120 #define SVR_LS2080A 0x870110 #define SVR_LS2085A 0x870100

If possible, please add other personality also

--prabhakar