From: Jagan Teki jagan@edgeble.ai
DW HDMI support Vendor PHY like Rockchip RK3328 Inno HDMI PHY.
Extend the vendor phy handling by adding platform phy hooks.
Signed-off-by: Jagan Teki jagan@edgeble.ai --- Changes for v3: - drop data - assign ops directly Changes for v2: - fix meson cfg
drivers/video/dw_hdmi.c | 10 +++++++++- drivers/video/meson/meson_dw_hdmi.c | 6 +++++- drivers/video/rockchip/rk_hdmi.c | 1 - drivers/video/sunxi/sunxi_dw_hdmi.c | 6 +++++- include/dw_hdmi.h | 8 +++++++- 5 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c index c4fbb18294..4914ba6146 100644 --- a/drivers/video/dw_hdmi.c +++ b/drivers/video/dw_hdmi.c @@ -988,7 +988,7 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid)
hdmi_av_composer(hdmi, edid);
- ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); + ret = hdmi->ops->phy_set(hdmi, edid->pixelclock.typ); if (ret) return ret;
@@ -1009,10 +1009,18 @@ int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) return 0; }
+static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { + .phy_set = dw_hdmi_phy_cfg, +}; + void dw_hdmi_init(struct dw_hdmi *hdmi) { uint ih_mute;
+ /* hook Synopsys PHYs ops */ + if (!hdmi->ops) + hdmi->ops = &dw_hdmi_synopsys_phy_ops; + /* * boot up defaults are: * hdmi_ih_mute = 0x03 (disabled) diff --git a/drivers/video/meson/meson_dw_hdmi.c b/drivers/video/meson/meson_dw_hdmi.c index 5db01904b5..259af1b457 100644 --- a/drivers/video/meson/meson_dw_hdmi.c +++ b/drivers/video/meson/meson_dw_hdmi.c @@ -375,6 +375,10 @@ static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi) return -ETIMEDOUT; }
+static const struct dw_hdmi_phy_ops dw_hdmi_meson_phy_ops = { + .phy_set = meson_dw_hdmi_phy_init, +}; + static int meson_dw_hdmi_probe(struct udevice *dev) { struct meson_dw_hdmi *priv = dev_get_priv(dev); @@ -397,7 +401,7 @@ static int meson_dw_hdmi_probe(struct udevice *dev)
priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24; - priv->hdmi.phy_set = meson_dw_hdmi_phy_init; + priv->hdmi.ops = &dw_hdmi_meson_phy_ops; if (meson_hdmi_is_compatible(priv, HDMI_COMPATIBLE_G12A)) priv->hdmi.reg_io_width = 1; else { diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index b75a174489..d5b5a529d2 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -90,7 +90,6 @@ int rk_hdmi_of_to_plat(struct udevice *dev) /* hdmi->i2c_clk_{high,low} are set up by the SoC driver */
hdmi->reg_io_width = 4; - hdmi->phy_set = dw_hdmi_phy_cfg;
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 0324a050d0..986e69d66b 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -369,6 +369,10 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) return 0; }
+static const struct dw_hdmi_phy_ops dw_hdmi_sunxi_phy_ops = { + .phy_set = sunxi_dw_hdmi_phy_cfg, +}; + static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) { struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); @@ -379,7 +383,7 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) hdmi->i2c_clk_high = 0xd8; hdmi->i2c_clk_low = 0xfe; hdmi->reg_io_width = 1; - hdmi->phy_set = sunxi_dw_hdmi_phy_cfg; + hdmi->ops = &dw_hdmi_sunxi_phy_ops;
ret = reset_get_bulk(dev, &priv->resets); if (ret) diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h index 8acae3839f..17bdd2dbf9 100644 --- a/include/dw_hdmi.h +++ b/include/dw_hdmi.h @@ -534,6 +534,12 @@ struct hdmi_data_info { struct hdmi_vmode video_mode; };
+struct dw_hdmi; + +struct dw_hdmi_phy_ops { + int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); +}; + struct dw_hdmi { ulong ioaddr; const struct hdmi_mpll_config *mpll_cfg; @@ -543,8 +549,8 @@ struct dw_hdmi { u8 reg_io_width; struct hdmi_data_info hdmi_data; struct udevice *ddc_bus; + const struct dw_hdmi_phy_ops *ops;
- int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); void (*write_reg)(struct dw_hdmi *hdmi, u8 val, int offset); u8 (*read_reg)(struct dw_hdmi *hdmi, int offset); };