Re: [U-Boot] [PATCH 2/5] fsl-ddr: clean up the ddr code for DDR3 controller

On Fri, Nov 21, 2008 at 2:31 AM, Dave Liu daveliu@freescale.com wrote:

• The DDR3 controller is expanding the bits for timing config
• Add the DDR3 32-bit bus mode support

Signed-off-by: Dave Liu daveliu@freescale.com

Applied to 85xx-next, thanks