The datasheet suggests that the state of an output pin can be read. In fact this does not seem to work, perhaps because we are also accessing the GPIO state through I/O instead of just memory-mapped.
Not to apply.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v2: None
drivers/gpio/intel_ich6_gpio.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c index 5cc86d7..204a4b4 100644 --- a/drivers/gpio/intel_ich6_gpio.c +++ b/drivers/gpio/intel_ich6_gpio.c @@ -49,6 +49,8 @@ struct ich6_bank_priv { #define GPIO_USESEL_OFFSET(x) (x) #define GPIO_IOSEL_OFFSET(x) (x + 4) #define GPIO_LVL_OFFSET(x) (x + 8) +#define IOPAD_VAL_OFFSET(x) (x + 8) +#define IINENB_SHIFT 2
#define IOPAD_MODE_MASK 0x7 #define IOPAD_PULL_ASSIGN_SHIFT 7 @@ -210,6 +212,7 @@ static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node) int val; int ret; const void *prop; + bool mode_gpio = false;
/* * GPIO node is not mandatory, so we only do the @@ -221,11 +224,13 @@ static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node) /* Do we want to force the GPIO mode? */ prop = fdt_getprop(gd->fdt_blob, pin_node, "mode-gpio", NULL); - if (prop) + if (prop) { _ich6_gpio_set_function(GPIO_USESEL_OFFSET (gpiobase) + gpio_offset[0], gpio_offset[1], 1); + mode_gpio = true; + }
val = fdtdec_get_int(gd->fdt_blob, pin_node, "direction", -1); @@ -270,8 +275,12 @@ static int _gpio_ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node) * be just ignored by the controller */ val = fdtdec_get_int(gd->fdt_blob, pin_node, "mode-func", -1); - if (val != -1) + if (val != -1) { clrsetbits_le32(iobase_addr, IOPAD_MODE_MASK, val); + } else if (mode_gpio) { + clrbits_le32(IOPAD_VAL_OFFSET(iobase_addr), + 1 << IINENB_SHIFT); + }
/* Configure the pull-up/down if needed */ val = fdtdec_get_int(gd->fdt_blob, pin_node, "pull-assign", -1);