Re: [U-Boot] [PATCH 06/11] Exynos542x: Change ambiguous function name set_l2cache

On 15 January 2015 at 06:42, Akshay Saraswat akshay.s@samsung.com wrote:

1. Renaming set_l2cache to configure_l2actlr in order to avoid misleading comprehensions. Apparently this name suggests that L2 cache is being set or initialized which is incorrect as per the code in this function.
2. Cleaning missed mrc for L2 control register.

Signed-off-by: Akshay Saraswat akshay.s@samsung.com

arch/arm/cpu/armv7/exynos/lowlevel_init.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c index d3c466e..688972b 100644 --- a/arch/arm/cpu/armv7/exynos/lowlevel_init.c +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c @@ -70,7 +70,7 @@ static void enable_smp(void)

• Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
• stalled for 1024 cycles to verify that its hazard condition still exists.

*/ -static void set_l2cache(void) +static void configure_l2actlr(void) { uint32_t val;

@@ -84,7 +84,6 @@ static void set_l2cache(void) mrc_l2_aux_ctlr(val); val |= (1 << 7); mcr_l2_aux_ctlr(val);

•           mrc_l2_ctlr(val);
    }
  

}

@@ -122,7 +121,7 @@ static void low_power_start(void)

    /* Set the CPU to SVC32 mode */
    svc32_mode_en();

•   set_l2cache();
  

•   configure_l2actlr();
  
    /* Invalidate L1 & TLB */
    val = 0x0;
  

@@ -175,7 +174,7 @@ static void power_down_core(void) static void secondary_cores_configure(void) { /* Setup L2 cache */

•   set_l2cache();
  

•   configure_l2actlr();
  
    /* Clear secondary boot iRAM base */
    writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
  

-- 1.9.1

Reviewed-by: Simon Glass sjg@chromium.org

Tested on snow, pit, pi Tested-by: Simon Glass sjg@chromium.org