On Sat, Feb 18, 2017 at 5:10 AM, Marek Vasut marex@denx.de wrote:
On 02/17/2017 09:56 AM, Ley Foon Tan wrote:
On Mon, Jan 23, 2017 at 12:18 PM, Marek Vasut marex@denx.de wrote:
On 01/10/2017 06:20 AM, Chee Tien Fong wrote:
From: Tien Fong Chee tien.fong.chee@intel.com
The drivers is restructured such common functions, gen5 functions, and arria10 functions are moved to clock_manager.c, clock_manager_gen5 and clock_manager_arria10 respectively.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dingnuyen@kernel.org Cc: Ching Liang See chin.liang.see@intel.com Cc: Tien Fong skywindctf@gmail.com
arch/arm/mach-socfpga/clock_manager.c | 752 +++++++--------- arch/arm/mach-socfpga/clock_manager_arria10.c | 954 +++++++++++++++++++++ .../{clock_manager.c => clock_manager_gen5.c} | 240 +----- arch/arm/mach-socfpga/include/mach/clock_manager.h | 356 ++++++-- 4 files changed, 1573 insertions(+), 729 deletions(-) create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c copy arch/arm/mach-socfpga/{clock_manager.c => clock_manager_gen5.c} (62%)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index aa71636..d209f7d 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -1,5 +1,5 @@ /*
- Copyright (C) 2013 Altera Corporation <www.altera.com>
*/
- Copyright (C) 2013-2016 Altera Corporation <www.altera.com>
- SPDX-License-Identifier: GPL-2.0+
@@ -7,416 +7,287 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock_manager.h> +#include <fdtdec.h>
DECLARE_GLOBAL_DATA_PTR;
+/* Function prototypes */ +/* Common prototypes */ +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); +static void cm_print_clock_quick_summary(void); +int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +void cm_wait_for_lock(uint32_t mask); +void cm_wait_for_fsm(void); +unsigned int cm_get_main_vco_clk_hz(void); +unsigned int cm_get_per_vco_clk_hz(void); +unsigned long cm_get_mpu_clk_hz(void);
static const struct socfpga_clock_manager *clock_manager_base = (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-static void cm_wait_for_lock(uint32_t mask) +/* Common functions */ +int set_cpu_clk_info(void) {
register uint32_t inter_val;uint32_t retry = 0;do {inter_val = readl(&clock_manager_base->inter) & mask;if (inter_val == mask)retry++;elseretry = 0;if (retry >= 10)break;} while (1);-}
/* Calculate the clock frequencies required for drivers */cm_get_l4_sp_clk_hz();cm_get_mmc_controller_clk_hz();-/* function to poll in the fsm busy bit */ -static void cm_wait_for_fsm(void) -{
while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY);-}
gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;gd->bd->bi_dsp_freq = 0;-/*
- function to write the bypass register which requires a poll of the
- busy bit
- */
-static void cm_write_bypass(uint32_t val) -{
writel(val, &clock_manager_base->bypass);cm_wait_for_fsm();-} +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
gd->bd->bi_ddr_freq = 0;What ? This cannot work ...
For A10, ddr controller is on fpga side and we don't need the ddr freq for ddr setup.
And if the user wants to know ? Any chance we can pass this info to the user ? I presume this is still a hard-IP controller, not some soft core thing ...
We can't provide this info to user now, because software can't read back or know the frequency of it now.
Regards Ley Foon