[U-Boot] FW: [PATCH 1/2] drivers/net/designware, do an explicit memory access instead of implicit, re-written assignments to use readl() and writel(), all of this as preperation for making the driver able to work in a cached environment (I$D$ support).

[[ ... to get attention again ... see below ...]] On 2/8/2013 6:22 PM, Frank Dols wrote:

Good afternoon Vipin and Albert, I where wondering, is there any review/update news on the patches I submitted a short while ago? Regards, Frank. Sorry, first excluded " u-boot@lists.denx.de" from this email to prevent from noice on mailing list.

There is no reason to remove the list. This is not noise I believe. Infact by including the list, you are intimating other developers that such work would be available soon

Albert, do you think any different.

Sorry, I have to clarify here a bit more. The descriptors are 16 bytes in length and a cache line is in most architectures more than 16 bytes in length (in our case either 32 or 64). This means that cached accesses is not an option for these descriptors. Background, two adjacent descriptors as be on one cache line may be owned by different entities (host cpu / network ip).

Yes, this is a problem and I can't think of a clean solution. Specially because u-boot (as of today) does not support non-cached memory

Albert?

Explicit cache calls that we are added in patch 2/2 are meant for payload of the package. And these are made cache line aligned with patch 1/2.

Yes, that is what I thought

Unfortunately we can't align the descriptors on cache line boundaries due to hardware limitations (for architectures with cache line longer than 16 bytes) !

Yes, I know that. The descriptors are 16 bytes and they need to be contiguous in memory

PS: I have not added the list but I strongly feel that this mail should also go to the uboot list

-Vipin

With kind regards, greetings, Frank.