[PATCH V2 08/12] arm: mach-k3: arm64-mmu: Refactor to be independent of board

4 Nov 2023

Refactor J721E J7200 definition to make this independent of board
macros.
Signed-off-by: Nishanth Menon nm@ti.com
---
 arch/arm/mach-k3/arm64-mmu.c | 50 ++++++++++++++++++------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index f8087d2421e7..8cb6614035a5 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -68,12 +68,11 @@ struct mm_region *mem_map = am654_mem_map;
#ifdef CONFIG_SOC_K3_J721E
-#ifdef CONFIG_TARGET_J721E_A72_EVM
-/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
-#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 6)
+#ifdef CONFIG_SOC_K3_J721E_J7200
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 5)
/* ToDo: Add 64bit IO */
-struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
+struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
    {
    	.virt = 0x0UL,
    	.phys = 0x0UL,
@@ -90,13 +89,13 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
    }, {
    	.virt = 0xa0000000UL,
    	.phys = 0xa0000000UL,
-		.size = 0x1bc00000UL,
+		.size = 0x04800000UL,
    	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
    		 PTE_BLOCK_NON_SHARE
    }, {
-		.virt = 0xbbc00000UL,
-		.phys = 0xbbc00000UL,
-		.size = 0x44400000UL,
+		.virt = 0xa4800000UL,
+		.phys = 0xa4800000UL,
+		.size = 0x5b800000UL,
    	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
    		 PTE_BLOCK_INNER_SHARE
    }, {
@@ -112,26 +111,21 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
    	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
    		 PTE_BLOCK_NON_SHARE |
    		 PTE_BLOCK_PXN | PTE_BLOCK_UXN
-	}, {
-		.virt = 0x4d80000000UL,
-		.phys = 0x4d80000000UL,
-		.size = 0x0002000000UL,
-		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
-			 PTE_BLOCK_INNER_SHARE
    }, {
    	/* List terminator */
    	0,
    }
 };
-struct mm_region *mem_map = j721e_mem_map;
-#endif /* CONFIG_TARGET_J721E_A72_EVM */
+struct mm_region *mem_map = j7200_mem_map;
-#ifdef CONFIG_TARGET_J7200_A72_EVM
-#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 5)
+#else /* CONFIG_SOC_K3_J721E_J7200 */
+
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 6)
/* ToDo: Add 64bit IO */
-struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
+struct mm_region j721e_mem_map[NR_MMU_REGIONS] = {
    {
    	.virt = 0x0UL,
    	.phys = 0x0UL,
@@ -148,13 +142,13 @@ struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
    }, {
    	.virt = 0xa0000000UL,
    	.phys = 0xa0000000UL,
-		.size = 0x04800000UL,
+		.size = 0x1bc00000UL,
    	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
    		 PTE_BLOCK_NON_SHARE
    }, {
-		.virt = 0xa4800000UL,
-		.phys = 0xa4800000UL,
-		.size = 0x5b800000UL,
+		.virt = 0xbbc00000UL,
+		.phys = 0xbbc00000UL,
+		.size = 0x44400000UL,
    	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
    		 PTE_BLOCK_INNER_SHARE
    }, {
@@ -170,14 +164,20 @@ struct mm_region j7200_mem_map[NR_MMU_REGIONS] = {
    	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
    		 PTE_BLOCK_NON_SHARE |
    		 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x4d80000000UL,
+		.phys = 0x4d80000000UL,
+		.size = 0x0002000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+			 PTE_BLOCK_INNER_SHARE
    }, {
    	/* List terminator */
    	0,
    }
 };
-struct mm_region *mem_map = j7200_mem_map;
-#endif /* CONFIG_TARGET_J7200_A72_EVM */
+struct mm_region *mem_map = j721e_mem_map;
+#endif /* CONFIG_SOC_K3_J721E_J7200 */
#endif /* CONFIG_SOC_K3_J721E */
-- 
2.37.2


    