From: Tien Fong Chee tien.fong.chee@intel.com
Add the defines for the reset manager and some basic reset functionality.
Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Cc: Marek Vasut marex@denx.de Cc: Dinh Nguyen dinguyen@kernel.org Cc: Chin Liang See chin.liang.see@intel.com Cc: Tien Fong skywindctf@gmail.com --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 65 ++++++++++++++++++++ arch/arm/mach-socfpga/reset_manager.c | 24 +++++++- 2 files changed, 88 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 2f070f2..6225118 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -15,6 +15,7 @@ void socfpga_bridges_reset(int enable); void socfpga_per_reset(u32 reset, int set); void socfpga_per_reset_all(void);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) struct socfpga_reset_manager { u32 status; u32 ctrl; @@ -28,6 +29,42 @@ struct socfpga_reset_manager { u32 padding2[12]; u32 tstscratch; }; +#else +struct socfpga_reset_manager { + u32 stat; + u32 ramstat; + u32 miscstat; + u32 ctrl; + u32 hdsken; + u32 hdskreq; + u32 hdskack; + u32 counts; + u32 mpu_mod_reset; + u32 per_mod_reset; /* stated as per0_mod_reset in A10 datasheet */ + u32 per2_mod_reset; /* stated as per1_mod_reset in A10 datasheet */ + u32 brg_mod_reset; + u32 misc_mod_reset; /* stated as sys_mod_reset in A10 datasheet */ + u32 coldmodrst; + u32 nrstmodrst; + u32 dbgmodrst; + u32 mpuwarmmask; + u32 per0warmmask; + u32 per1warmmask; + u32 brgwarmmask; + u32 syswarmmask; + u32 nrstwarmmask; + u32 l3warmmask; + u32 tststa; + u32 tstscratch; + u32 hdsktimeout; + u32 hmcintr; + u32 hmcintren; + u32 hmcintrens; + u32 hmcintrenr; + u32 hmcgpout; + u32 hmcgpin; +}; +#endif
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 @@ -55,6 +92,7 @@ struct socfpga_reset_manager { #define RSTMGR_BANK(_reset) \ (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows: * 0 ... mpumodrst @@ -75,6 +113,33 @@ struct socfpga_reset_manager { #define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22) #define RSTMGR_DMA RSTMGR_DEFINE(1, 28) #define RSTMGR_SDR RSTMGR_DEFINE(1, 29) +#else +/* + * SocFPGA Arria10 reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... per0modrst + * 2 ... per1modrst + * 3 ... brgmodrst + * 4 ... sysmodrst + */ +#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) +#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) +#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) +#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) +#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2) +#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3) +#define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4) +#define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5) +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) +#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) +#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) +#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) +#define RSTMGR_QSPI RSTMGR_DEFINE(1, 6) +#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) +#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) +#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6) +#endif
/* Create a human-readable reference to SoCFPGA reset. */ #define SOCFPGA_RESET(_name) RSTMGR_##_name diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c index b6beaa2..d0ff6c4 100644 --- a/arch/arm/mach-socfpga/reset_manager.c +++ b/arch/arm/mach-socfpga/reset_manager.c @@ -18,7 +18,9 @@ static const struct socfpga_reset_manager *reset_manager_base = static struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-/* Assert or de-assert SoCFPGA reset manager reset. */ +/* + * Assert or de-assert SoCFPGA reset manager reset. + */ void socfpga_per_reset(u32 reset, int set) { const void *reg; @@ -46,13 +48,29 @@ void socfpga_per_reset(u32 reset, int set) * Assert reset on every peripheral but L4WD0. * Watchdog must be kept intact to prevent glitches * and/or hangs. + * For the Arria10, we disable all the peripherals except L4 watchdog0, + * L4 Timer 0, and ECC. */ void socfpga_per_reset_all(void) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
writel(~l4wd0, &reset_manager_base->per_mod_reset); writel(0xffffffff, &reset_manager_base->per2_mod_reset); +#else + const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) | + (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0)))); + + unsigned mask_ecc_ocp = 0x0000FF00; + + /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */ + writel(~l4wd0, &reset_manager_base->per1_mod_reset); + setbits_le32(&reset_manager_base->per0_mod_reset, ~mask_ecc_ocp); + + /* Finally disable the ECC_OCP */ + setbits_le32(&reset_manager_base->per0_mod_reset, mask_ecc_ocp); +#endif }
/* @@ -71,6 +89,7 @@ void reset_cpu(ulong addr) ; }
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) /* * Release peripherals from reset based on handoff */ @@ -78,6 +97,7 @@ void reset_deassert_peripherals_handoff(void) { writel(0, &reset_manager_base->per_mod_reset); } +#endif
#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) void socfpga_bridges_reset(int enable) @@ -92,6 +112,7 @@ void socfpga_bridges_reset(int enable)
void socfpga_bridges_reset(int enable) { +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | L3REGS_REMAP_HPS2FPGA_MASK | L3REGS_REMAP_OCRAM_MASK; @@ -116,5 +137,6 @@ void socfpga_bridges_reset(int enable) /* Remap the bridges into memory map */ writel(l3mask, SOCFPGA_L3REGS_ADDRESS); } +#endif } #endif