On 15.08.22 08:35, Holger Brunck wrote:
These boards are out of maintenance and can be removed.
Signed-off-by: Holger Brunck holger.brunck@hitachienergy.com
Reviewed-by: Stefan Roese sr@denx.de
Thanks, Stefan
arch/arm/dts/Makefile | 1 - arch/arm/dts/kirkwood-km_common.dtsi | 48 --- arch/arm/dts/kirkwood-km_kirkwood.dts | 53 --- board/keymile/Kconfig | 1 - board/keymile/km_arm/Kconfig | 86 ----- board/keymile/km_arm/MAINTAINERS | 11 - board/keymile/km_arm/Makefile | 11 - board/keymile/km_arm/fpga_config.c | 255 -------------- board/keymile/km_arm/km_arm.c | 520 ----------------------------- board/keymile/km_arm/kwbimage-memphis.cfg | 179 ---------- board/keymile/km_arm/kwbimage.cfg | 161 --------- board/keymile/km_arm/kwbimage_128M16_1.cfg | 257 -------------- board/keymile/km_arm/kwbimage_256M8_1.cfg | 257 -------------- board/keymile/scripts/develop-common.txt | 2 +- configs/km_kirkwood_128m16_defconfig | 81 ----- configs/km_kirkwood_defconfig | 81 ----- configs/km_kirkwood_pci_defconfig | 81 ----- configs/kmcoge5un_defconfig | 84 ----- configs/kmnusa_defconfig | 85 ----- configs/kmsuse2_defconfig | 85 ----- include/configs/km/km_arm.h | 158 --------- include/configs/km_kirkwood.h | 118 ------- scripts/config_whitelist.txt | 1 - 23 files changed, 1 insertion(+), 2615 deletions(-) delete mode 100644 arch/arm/dts/kirkwood-km_common.dtsi delete mode 100644 arch/arm/dts/kirkwood-km_kirkwood.dts delete mode 100644 board/keymile/km_arm/Kconfig delete mode 100644 board/keymile/km_arm/MAINTAINERS delete mode 100644 board/keymile/km_arm/Makefile delete mode 100644 board/keymile/km_arm/fpga_config.c delete mode 100644 board/keymile/km_arm/km_arm.c delete mode 100644 board/keymile/km_arm/kwbimage-memphis.cfg delete mode 100644 board/keymile/km_arm/kwbimage.cfg delete mode 100644 board/keymile/km_arm/kwbimage_128M16_1.cfg delete mode 100644 board/keymile/km_arm/kwbimage_256M8_1.cfg delete mode 100644 configs/km_kirkwood_128m16_defconfig delete mode 100644 configs/km_kirkwood_defconfig delete mode 100644 configs/km_kirkwood_pci_defconfig delete mode 100644 configs/kmcoge5un_defconfig delete mode 100644 configs/kmnusa_defconfig delete mode 100644 configs/kmsuse2_defconfig delete mode 100644 include/configs/km/km_arm.h delete mode 100644 include/configs/km_kirkwood.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7330121..3f5bfca 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -58,7 +58,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-ib62x0.dtb \ kirkwood-iconnect.dtb \ kirkwood-is2.dtb \
- kirkwood-km_kirkwood.dtb \ kirkwood-lsxhl.dtb \ kirkwood-lschlv2.dtb \ kirkwood-net2big.dtb \
diff --git a/arch/arm/dts/kirkwood-km_common.dtsi b/arch/arm/dts/kirkwood-km_common.dtsi deleted file mode 100644 index 9d0fc51..0000000 --- a/arch/arm/dts/kirkwood-km_common.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ {
- chosen {
bootargs = "console=ttyS0,115200n8 earlyprintk";stdout-path = &uart0;- };
- ocp@f1000000 {
pinctrl: pin-controller@10000 {pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;pinctrl-names = "default";pmx_i2c_gpio_sda: pmx-gpio-sda {marvell,pins = "mpp8";marvell,function = "gpio";};pmx_i2c_gpio_scl: pmx-gpio-scl {marvell,pins = "mpp9";marvell,function = "gpio";};};serial@12000 {status = "okay";clock-frequency = <200000000>;};- };
- i2c {
compatible = "i2c-gpio";gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */&gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */i2c-gpio,delay-us = <2>; /* ~100 kHz */- };
-};
-&nand {
- status = "okay";
- chip-delay = <25>;
-};
-&pciec {
status = "okay";-};
-&pcie0 {
- status = "okay";
-}; diff --git a/arch/arm/dts/kirkwood-km_kirkwood.dts b/arch/arm/dts/kirkwood-km_kirkwood.dts deleted file mode 100644 index b2c0209..0000000 --- a/arch/arm/dts/kirkwood-km_kirkwood.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/;
-#include "kirkwood.dtsi" -#include "kirkwood-98dx4122.dtsi" -#include "kirkwood-km_common.dtsi"
-/ {
- model = "Keymile Kirkwood Reference Design";
- compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
- memory {
device_type = "memory";reg = <0x00000000 0x08000000>;- };
- aliases {
spi0 = &spi0;- };
-};
-&mdio {
- status = "okay";
- ethphy0: ethernet-phy@0 {
reg = <0>;- };
-};
-ð0 {
- status = "okay";
- ethernet0-port@0 {
phy-handle = <ðphy0>;- };
-};
-&spi0 {
- status = "okay";
- flash@0 {
#address-cells = <1>;#size-cells = <1>;compatible = "st,m25p80", "jedec,spi-nor", "spi-flash";reg = <0>;spi-max-frequency = <33000000>;mode = <3>;partition@uboot {reg = <0x000000 0x0c0000>;label = "uboot";};- };
-}; diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index f22faee..9f78443 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -167,7 +167,6 @@ config PG_WCOM_UBOOT_UPDATE
source "board/keymile/km83xx/Kconfig" source "board/keymile/kmcent2/Kconfig" -source "board/keymile/km_arm/Kconfig" source "board/keymile/pg-wcom-ls102xa/Kconfig"
endmenu diff --git a/board/keymile/km_arm/Kconfig b/board/keymile/km_arm/Kconfig deleted file mode 100644 index 9d222d7..0000000 --- a/board/keymile/km_arm/Kconfig +++ /dev/null @@ -1,86 +0,0 @@ -menu "KM ARM Options"
- depends on ARM
-config KM_FPGA_CONFIG
- bool "FPGA Configuration"
- help
Include capability to change FPGA configuration.-config KM_FPGA_FORCE_CONFIG
- bool "FPGA reconfiguration"
- help
If yes we force to reconfigure the FPGA always-config KM_FPGA_NO_RESET
- bool "FPGA skip reset"
- help
If yes we skip triggering a reset of the FPGA-config KM_ENV_IS_IN_SPI_NOR
- bool "Environment in SPI NOR"
- help
Put the U-Boot environment in the SPI NOR flash.-config KM_PIGGY4_88E6061
- bool "Piggy via Switch 88E6061"
- help
The Piggy4 board is connected via a Marvell 88E6061 switch.-config KM_PIGGY4_88E6352
- bool "Piggy via Switch 88E6352"
- help
The Piggy4 board is connected via a Marvell 88E6352 switch.-endmenu
-if TARGET_KM_KIRKWOOD
-config SYS_BOARD
- default "km_arm"
-config SYS_VENDOR
- default "keymile"
-config SYS_CONFIG_NAME
- default "km_kirkwood"
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select BOARD_LATE_INIT
- select DM
- select DM_ETH
- select DM_SERIAL
- select DM_SPI
- select DM_SPI_FLASH
- select USB
- select USB_EHCI_HCD
- select USB_EHCI_MARVELL
- imply CMD_CRAMFS
- imply CMD_DIAG
- imply FS_CRAMFS
- imply CMD_USB
-choice
- prompt "Board model"
-config KM_COGE5UN
- bool "Hitachi Power Grids COGE5UN"
-config KM_KIRKWOOD_128M16
- bool "Hitachi Power Grids Kirkwood 128M16"
-config KM_KIRKWOOD
- bool "Hitachi Power Grids Kirkwood"
-config KM_KIRKWOOD_PCI
- bool "Hitachi Power Grids Kirkwood PCI"
-config KM_NUSA
- bool "Hitachi Power Grids Kirkwood (NUSA)"
-config KM_SUSE2
- bool "Hitachi Power Grids Kirkwood (SUSE2)"
-endchoice
-endif diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS deleted file mode 100644 index bc6858b..0000000 --- a/board/keymile/km_arm/MAINTAINERS +++ /dev/null @@ -1,11 +0,0 @@ -KM_ARM BOARD -M: Holger Brunck holger.brunck@hitachienergy.com -S: Maintained -F: board/keymile/km_arm/ -F: include/configs/km_kirkwood.h -F: configs/km_kirkwood_defconfig -F: configs/km_kirkwood_128m16_defconfig -F: configs/km_kirkwood_pci_defconfig -F: configs/kmcoge5un_defconfig -F: configs/kmnusa_defconfig -F: configs/kmsuse2_defconfig diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile deleted file mode 100644 index 79ccc76..0000000 --- a/board/keymile/km_arm/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Prafulla Wadaskar prafulla@marvell.com
-obj-y := km_arm.o ../common/common.o ../common/ivm.o
-ifdef CONFIG_KM_FPGA_CONFIG -obj-y += fpga_config.o -endif diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c deleted file mode 100644 index 839b162..0000000 --- a/board/keymile/km_arm/fpga_config.c +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- (C) Copyright 2012
- Valentin Lontgchamp, Keymile AG, valentin.longchamp@keymile.com
- */
-#include <common.h> -#include <i2c.h> -#include <linux/delay.h> -#include <linux/errno.h>
-/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ -#define KM_XLX_PROGRAM_B_PIN 39
-#define BOCO_ADDR 0x10
-#define ID_REG 0x00 -#define BOCO2_ID 0x5b
-static int check_boco2(void) -{
- int ret;
- u8 id;
- ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1);
- if (ret) {
printf("%s: error reading the BOCO id !!\n", __func__);return ret;- }
- return (id == BOCO2_ID);
-}
-static int boco_clear_bits(u8 reg, u8 flags) -{
- int ret;
- u8 regval;
- /* give access to the EEPROM from FPGA */
- ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
- if (ret) {
printf("%s: error reading the BOCO @%#x !!\n",__func__, reg);return ret;- }
- regval &= ~flags;
- ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
- if (ret) {
printf("%s: error writing the BOCO @%#x !!\n",__func__, reg);return ret;- }
- return 0;
-}
-static int boco_set_bits(u8 reg, u8 flags) -{
- int ret;
- u8 regval;
- /* give access to the EEPROM from FPGA */
- ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1);
- if (ret) {
printf("%s: error reading the BOCO @%#x !!\n",__func__, reg);return ret;- }
- regval |= flags;
- ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1);
- if (ret) {
printf("%s: error writing the BOCO @%#x !!\n",__func__, reg);return ret;- }
- return 0;
-}
-#define SPI_REG 0x06 -#define CFG_EEPROM 0x02 -#define FPGA_PROG 0x04 -#define FPGA_INIT_B 0x10 -#define FPGA_DONE 0x20
-#ifndef CONFIG_KM_FPGA_FORCE_CONFIG -static int fpga_done(void) -{
- int ret = 0;
- u8 regval;
- /* this is only supported with the boco2 design */
- if (!check_boco2())
return 0;- ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1);
- if (ret) {
printf("%s: error reading the BOCO @%#x !!\n",__func__, SPI_REG);return 0;- }
- return regval & FPGA_DONE ? 1 : 0;
-} -#endif /* CONFIG_KM_FPGA_FORCE_CONFIG */
-static int skip;
-int trigger_fpga_config(void) -{
- int ret = 0;
- skip = 0;
-#ifndef CONFIG_KM_FPGA_FORCE_CONFIG
- /* if the FPGA is already configured, we do not want to
* reconfigure it*/- skip = 0;
- if (fpga_done()) {
printf("PCIe FPGA config: skipped\n");skip = 1;return 0;- }
-#endif /* CONFIG_KM_FPGA_FORCE_CONFIG */
- if (check_boco2()) {
/* we have a BOCO2, this has to be triggered here *//* make sure the FPGA_can access the EEPROM */ret = boco_clear_bits(SPI_REG, CFG_EEPROM);if (ret)return ret;/* trigger the config start */ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B);if (ret)return ret;/* small delay for the pulse */udelay(10);/* up signal for pulse end */ret = boco_set_bits(SPI_REG, FPGA_PROG);if (ret)return ret;/* finally, raise INIT_B to remove the config delay */ret = boco_set_bits(SPI_REG, FPGA_INIT_B);if (ret)return ret;- } else {
/* we do it the old way, with the gpio pin */kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1);kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0);/* small delay for the pulse */udelay(10);kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN);- }
- return 0;
-}
-int wait_for_fpga_config(void) -{
- int ret = 0;
- u8 spictrl;
- u32 timeout = 20000;
- if (skip)
return 0;- if (!check_boco2()) {
/* we do not have BOCO2, this is not really used */return 0;- }
- printf("PCIe FPGA config:");
- do {
ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1);if (ret) {printf("%s: error reading the BOCO spictrl !!\n",__func__);return ret;}if (timeout-- == 0) {printf(" FPGA_DONE timeout\n");return -EFAULT;}udelay(10);- } while (!(spictrl & FPGA_DONE));
- printf(" done\n");
- return 0;
-}
-#if defined(CONFIG_KM_FPGA_NO_RESET) -int fpga_reset(void) -{
- /* no dedicated reset pin for FPGA */
- return 0;
-} -#else
-#define PRST1 0x4 -#define PCIE_RST 0x10 -#define TRAFFIC_RST 0x04
-int fpga_reset(void) -{
- int ret = 0;
- u8 resets;
- if (!check_boco2()) {
/* we do not have BOCO2, this is not really used */return 0;- }
- /* if we have skipped, we only want to reset the PCIe part */
- resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST;
- ret = boco_clear_bits(PRST1, resets);
- if (ret)
return ret;- /* small delay for the pulse */
- udelay(10);
- ret = boco_set_bits(PRST1, resets);
- if (ret)
return ret;- return 0;
-} -#endif
-/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
- is available from the Bobcat SPI bus
- */
-int toggle_eeprom_spi_bus(void) -{
- int ret = 0;
- if (!check_boco2()) {
/* we do not have BOCO2, this is not really used */return 0;- }
- ret = boco_set_bits(SPI_REG, CFG_EEPROM);
- if (ret)
return ret;- return 0;
-} diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c deleted file mode 100644 index e9af090..0000000 --- a/board/keymile/km_arm/km_arm.c +++ /dev/null @@ -1,520 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Prafulla Wadaskar prafulla@marvell.com
- (C) Copyright 2009
- Stefan Roese, DENX Software Engineering, sr@denx.de.
- (C) Copyright 2010
- Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-#include <common.h> -#include <env.h> -#include <i2c.h> -#include <init.h> -#include <nand.h> -#include <net.h> -#include <netdev.h> -#include <miiphy.h> -#include <spi.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h>
-#include "../common/common.h"
-DECLARE_GLOBAL_DATA_PTR;
-/*
- BOCO FPGA definitions
- */
-#define BOCO 0x10 -#define REG_CTRL_H 0x02 -#define MASK_WRL_UNITRUN 0x01 -#define MASK_RBX_PGY_PRESENT 0x40 -#define REG_IRQ_CIRQ2 0x2d -#define MASK_RBI_DEFECT_16 0x01
-/*
- PHY registers definitions
- */
-#define PHY_MARVELL_OUI 0x5043 -#define PHY_MARVELL_88E1118_MODEL 0x0022 -#define PHY_MARVELL_88E1118R_MODEL 0x0024
-#define PHY_MARVELL_PAGE_REG 0x0016 -#define PHY_MARVELL_DEFAULT_PAGE 0x0000
-#define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003 -#define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010
-#define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000 -#define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7 << 0) -#define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3 << 4) -#define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0 << 8)
-/* I/O pin to erase flash RGPP09 = MPP43 */ -#define KM_FLASH_ERASE_ENABLE 43
-/* Multi-Purpose Pins Functionality configuration */ -static const u32 kwmpp_config[] = {
- MPP0_NF_IO2,
- MPP1_NF_IO3,
- MPP2_NF_IO4,
- MPP3_NF_IO5,
- MPP4_NF_IO6,
- MPP5_NF_IO7,
- MPP6_SYSRST_OUTn,
- MPP7_PEX_RST_OUTn,
-#if defined(CONFIG_SYS_I2C_SOFT)
- MPP8_GPIO, /* SDA */
- MPP9_GPIO, /* SCL */
-#endif
- MPP10_UART0_TXD,
- MPP11_UART0_RXD,
- MPP12_GPO, /* Reserved */
- MPP13_UART1_TXD,
- MPP14_UART1_RXD,
- MPP15_GPIO, /* Not used */
- MPP16_GPIO, /* Not used */
- MPP17_GPIO, /* Reserved */
- MPP18_NF_IO0,
- MPP19_NF_IO1,
- MPP20_GPIO,
- MPP21_GPIO,
- MPP22_GPIO,
- MPP23_GPIO,
- MPP24_GPIO,
- MPP25_GPIO,
- MPP26_GPIO,
- MPP27_GPIO,
- MPP28_GPIO,
- MPP29_GPIO,
- MPP30_GPIO,
- MPP31_GPIO,
- MPP32_GPIO,
- MPP33_GPIO,
- MPP34_GPIO, /* CDL1 (input) */
- MPP35_GPIO, /* CDL2 (input) */
- MPP36_GPIO, /* MAIN_IRQ (input) */
- MPP37_GPIO, /* BOARD_LED */
- MPP38_GPIO, /* Piggy3 LED[1] */
- MPP39_GPIO, /* Piggy3 LED[2] */
- MPP40_GPIO, /* Piggy3 LED[3] */
- MPP41_GPIO, /* Piggy3 LED[4] */
- MPP42_GPIO, /* Piggy3 LED[5] */
- MPP43_GPIO, /* Piggy3 LED[6] */
- MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */
- MPP45_GPIO, /* Piggy3 LED[8] */
- MPP46_GPIO, /* Reserved */
- MPP47_GPIO, /* Reserved */
- MPP48_GPIO, /* Reserved */
- MPP49_GPIO, /* SW_INTOUTn */
- 0
-};
-static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
-#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) -/*
- All boards with PIGGY4 connected via a simple switch have ethernet always
- present.
- */
-int ethernet_present(void) -{
- return 1;
-} -#else -int ethernet_present(void) -{
- uchar buf;
- int ret = 0;
- if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
printf("%s: Error reading Boco\n", __func__);return -1;- }
- if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT)
ret = 1;- return ret;
-} -#endif
-static int initialize_unit_leds(void) -{
- /*
* Init the unit LEDs per default they all are* ok apart from bootstat*/- uchar buf;
- if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
printf("%s: Error reading Boco\n", __func__);return -1;- }
- buf |= MASK_WRL_UNITRUN;
- if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) {
printf("%s: Error writing Boco\n", __func__);return -1;- }
- return 0;
-}
-static void set_bootcount_addr(void) -{
- uchar buf[32];
- unsigned int bootcountaddr;
- bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR;
- sprintf((char *)buf, "0x%x", bootcountaddr);
- env_set("bootcountaddr", (char *)buf);
-}
-int misc_init_r(void) -{
- ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
CONFIG_PIGGY_MAC_ADDRESS_OFFSET);- initialize_unit_leds();
- set_km_env();
- set_bootcount_addr();
- return 0;
-}
-int board_early_init_f(void) -{ -#if defined(CONFIG_SYS_I2C_SOFT)
- u32 tmp;
- /* set the 2 bitbang i2c pins as output gpios */
- tmp = readl(MVEBU_GPIO0_BASE + 4);
- writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS), MVEBU_GPIO0_BASE + 4);
-#endif
- /* adjust SDRAM size for bank 0 */
- mvebu_sdram_size_adjust(0);
- kirkwood_mpp_conf(kwmpp_config, NULL);
- return 0;
-}
-int board_init(void) -{
- /* address of boot parameters */
- gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
- /*
* The KM_FLASH_GPIO_PIN switches between using a* NAND or a SPI FLASH. Set this pin on start* to NAND mode.*/- kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1);
- kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1);
-#if defined(CONFIG_SYS_I2C_SOFT)
- /*
* Reinit the GPIO for I2C Bitbang driver so that the now* available gpio framework is consistent. The calls to* direction output in are not necessary, they are already done in* board_early_init_f*/- kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1);
- kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1);
-#endif
-#if defined(CONFIG_SYS_EEPROM_WREN)
- kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38);
- kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1);
-#endif
-#if defined(CONFIG_KM_FPGA_CONFIG)
- trigger_fpga_config();
-#endif
- return 0;
-}
-int board_late_init(void) -{ -#if defined(CONFIG_KM_COGE5UN)
- u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE);
- /* if pin 1 do full erase */
- if (dip_switch != 0) {
/* start bootloader */puts("DIP: Enabled\n");env_set("actual_bank", "0");- }
-#endif
-#if defined(CONFIG_KM_FPGA_CONFIG)
- wait_for_fpga_config();
- fpga_reset();
- toggle_eeprom_spi_bus();
-#endif
- return 0;
-}
-static const u32 spi_mpp_config[] = {
- MPP1_SPI_MOSI,
- MPP2_SPI_SCK,
- MPP3_SPI_MISO,
- 0
-};
-static u32 spi_mpp_backup[4];
-int mvebu_board_spi_claim_bus(struct udevice *dev) -{
- spi_mpp_backup[3] = 0;
- /* set new spi mpp config and save current one */
- kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup);
- kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0);
- return 0;
-}
-int mvebu_board_spi_release_bus(struct udevice *dev) -{
- /* restore saved mpp config */
- kirkwood_mpp_conf(spi_mpp_backup, NULL);
- kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1);
- return 0;
-}
-#if (defined(CONFIG_KM_PIGGY4_88E6061))
-#define PHY_LED_SEL_REG 0x18 -#define PHY_LED0_LINK (0x5) -#define PHY_LED1_ACT (0x8 << 4) -#define PHY_LED2_INT (0xe << 8) -#define PHY_SPEC_CTRL_REG 0x1c -#define PHY_RGMII_CLK_STABLE (0x1 << 10) -#define PHY_CLSA (0x1 << 1)
-/* Configure and enable MV88E3018 PHY */ -void reset_phy(void) -{
- char *name = "egiga0";
- unsigned short reg;
- if (miiphy_set_current_dev(name))
return;- /* RGMII clk transition on data stable */
- if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, ®))
printf("Error reading PHY spec ctrl reg\n");- if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG,
reg | PHY_RGMII_CLK_STABLE | PHY_CLSA))printf("Error writing PHY spec ctrl reg\n");- /* leds setup */
- if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG,
PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT))printf("Error writing PHY LED reg\n");- /* reset the phy */
- miiphy_reset(name, CONFIG_PHY_BASE_ADR);
-} -#elif defined(CONFIG_KM_PIGGY4_88E6352)
-#include <mv88e6352.h>
-#if defined(CONFIG_KM_NUSA) -struct mv88e_sw_reg extsw_conf[] = {
- /*
* port 0, PIGGY4, autoneg* first the fix for the 1000Mbits Autoneg, this is from* a Marvell errata, the regs are undocumented*/- { PHY(0), PHY_PAGE, AN1000FIX_PAGE },
- { PHY(0), PHY_STATUS, AN1000FIX },
- { PHY(0), PHY_PAGE, 0 },
- /* now the real port and phy configuration */
- { PORT(0), PORT_PHY, NO_SPEED_FOR },
- { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
- { PHY(0), PHY_1000_CTRL, NO_ADV },
- { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN },
- { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST |
FULL_DUPLEX },- /* port 1, unused */
- { PORT(1), PORT_CTRL, PORT_DIS },
- { PHY(1), PHY_CTRL, PHY_PWR_DOWN },
- { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
- /* port 2, unused */
- { PORT(2), PORT_CTRL, PORT_DIS },
- { PHY(2), PHY_CTRL, PHY_PWR_DOWN },
- { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
- /* port 3, unused */
- { PORT(3), PORT_CTRL, PORT_DIS },
- { PHY(3), PHY_CTRL, PHY_PWR_DOWN },
- { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
- /* port 4, ICNEV, SerDes, SGMII */
- { PORT(4), PORT_STATUS, NO_PHY_DETECT },
- { PORT(4), PORT_PHY, SPEED_1000_FOR },
- { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
- { PHY(4), PHY_CTRL, PHY_PWR_DOWN },
- { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN },
- /* port 5, CPU_RGMII */
- { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN |
FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX |FULL_DPX_FOR | SPEED_1000_FOR },- { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL },
- /* port 6, unused, this port has no phy */
- { PORT(6), PORT_CTRL, PORT_DIS },
-}; -#else -struct mv88e_sw_reg extsw_conf[] = {}; -#endif
-void reset_phy(void) -{ -#if defined(CONFIG_KM_MVEXTSW_ADDR)
- char *name = "egiga0";
- if (miiphy_set_current_dev(name))
return;- mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf,
ARRAY_SIZE(extsw_conf));- mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR);
-#endif -}
-#else -/* Configure and enable MV88E1118 PHY on the piggy*/ -void reset_phy(void) -{
- unsigned int oui;
- unsigned char model, rev;
- char *name = "egiga0";
- if (miiphy_set_current_dev(name))
return;- /* reset the phy */
- miiphy_reset(name, CONFIG_PHY_BASE_ADR);
- /* get PHY model */
- if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev))
return;- /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */
- if (oui == PHY_MARVELL_OUI &&
model == PHY_MARVELL_88E1118R_MODEL) {/* set page register to 3 */if (miiphy_write(name, CONFIG_PHY_BASE_ADR,PHY_MARVELL_PAGE_REG,PHY_MARVELL_88E1118R_LED_CTRL_PAGE))printf("Error writing PHY page reg\n");/** leds setup as printed on PCB:* LED2 (Link): 0x0 (On Link, Off No Link)* LED1 (Activity): 0x3 (On Activity, Off No Activity)* LED0 (Speed): 0x7 (On 1000 MBits, Off Else)*/if (miiphy_write(name, CONFIG_PHY_BASE_ADR,PHY_MARVELL_88E1118R_LED_CTRL_REG,PHY_MARVELL_88E1118R_LED_CTRL_RESERVED |PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB |PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT |PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK))printf("Error writing PHY LED reg\n");/* set page register back to 0 */if (miiphy_write(name, CONFIG_PHY_BASE_ADR,PHY_MARVELL_PAGE_REG,PHY_MARVELL_DEFAULT_PAGE))printf("Error writing PHY page reg\n");- }
-} -#endif
-#if defined(CONFIG_HUSH_INIT_VAR) -int hush_init_var(void) -{
- ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
- return 0;
-} -#endif
-#if defined(CONFIG_SYS_I2C_SOFT) -void set_sda(int state) -{
- I2C_ACTIVE;
- I2C_SDA(state);
-}
-void set_scl(int state) -{
- I2C_SCL(state);
-}
-int get_sda(void) -{
- I2C_TRISTATE;
- return I2C_READ;
-}
-int get_scl(void) -{
- return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0;
-} -#endif
-#if defined(CONFIG_POST)
-#define KM_POST_EN_L 44 -#define POST_WORD_OFF 8
-int post_hotkeys_pressed(void) -{
- if (IS_ENABLED(CONFIG_KM_COGE5UN))
return kw_gpio_get_value(KM_POST_EN_L);- else
return !kw_gpio_get_value(KM_POST_EN_L);-}
-ulong post_word_load(void) -{
- void *addr = (void *)(gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
- return in_le32(addr);
-} -void post_word_store(ulong value) -{
- void *addr = (void *)(gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF);
- out_le32(addr, value);
-}
-int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) -{
- *vstart = CONFIG_SYS_SDRAM_BASE;
- /* we go up to relocation plus a 1 MB margin */
- *size = CONFIG_SYS_TEXT_BASE - (1 << 20);
- return 0;
-} -#endif
-#if defined(CONFIG_SYS_EEPROM_WREN) -int eeprom_write_enable(unsigned int dev_addr, int state) -{
- kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state);
- return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP);
-} -#endif diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg deleted file mode 100644 index d850e10..0000000 --- a/board/keymile/km_arm/kwbimage-memphis.cfg +++ /dev/null @@ -1,179 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2010 -# Heiko Schocher, DENX Software Engineering, hs@denx.de. -# -# (C) Copyright 2011 -# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -#
-# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash
-DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: MPPSel0 2, NF_IO[2] -# bit 7-4: MPPSel1 2, NF_IO[3] -# bit 12-8: MPPSel2 2, NF_IO[4] -# bit 15-12: MPPSel3 2, NF_IO[5] -# bit 19-16: MPPSel4 1, NF_IO[6] -# bit 23-20: MPPSel5 1, NF_IO[7] -# bit 27-24: MPPSel6 1, SYSRST_O -# bit 31-28: MPPSel7 0, GPO[7]
-DATA 0xFFD10004 0x03303300
-DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: MPPSel16 0, GPIO[16] -# bit 7-4: MPPSel17 0, GPIO[17] -# bit 12-8: MPPSel18 1, NF_IO[0] -# bit 15-12: MPPSel19 1, NF_IO[1] -# bit 19-16: MPPSel20 0, GPIO[20] -# bit 23-20: MPPSel21 0, GPIO[21] -# bit 27-24: MPPSel22 0, GPIO[22] -# bit 31-28: MPPSel23 0, GPIO[23]
-DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
-# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
-#Dram initalization -DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register -# bit13-0: 0x4E0 (DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01
-DATA 0xFFD01404 0x38543000 # DDR Controller Control Low -# bit 3-0: 0 reserved -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay
-DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP
-DATA 0xFFD0140C 0x00000A3E # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required
-DATA 0xFFD01410 0x00000001 # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 00, Cs0size=2Gb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required
-DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required
-DATA 0xFFD0141C 0x00000652 # DDR Mode -DATA 0xFFD01420 0x00000006 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strenght reduced -# bit2: 1, DDR ODT control lsd disabled -# bit5-3: 000, required -# bit6: 0, DDR ODT control msb disabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add a sample stage -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required
-DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low -# bit3-0 : 0000, required -# bit7-4 : 0010, M_ODT assertion 2 cycles after read -# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read -# bit15-12: 0100, internal ODT assertion 4 cycles after read -# bit19-16: 1000, internal ODT de-assertion 8 cycles after read -# bit31-20: 0 , required
-DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High -# bit3-0 : 0001, M_ODT assertion same cycle as write -# bit7-4 : 0101, M_ODT de-assertion x cycles after write -# bit11-8 : 0100, internal ODT assertion x cycles after write -# bit15-12: 1000, internal ODT de-assertion x cycles after write
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB)
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 00, ODT1 controlled by register -# bit31-4: zero, required
-DATA 0xFFD0149C 0x0000F801 # CPU ODT Control -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 -# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr -# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm -# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm -# bit14 :1, STARTBURST ODT enabled -# bit15 :1, Use ODT Block
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit0=1, enable DDR init upon this register write
-# End of Header extension -DATA 0x0 0x0 diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg deleted file mode 100644 index 6b62ce0..0000000 --- a/board/keymile/km_arm/kwbimage.cfg +++ /dev/null @@ -1,161 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2010 -# Heiko Schocher, DENX Software Engineering, hs@denx.de. -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -#
-# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash
-DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: MPPSel0 2, NF_IO[2] -# bit 7-4: MPPSel1 2, NF_IO[3] -# bit 12-8: MPPSel2 2, NF_IO[4] -# bit 15-12: MPPSel3 2, NF_IO[5] -# bit 19-16: MPPSel4 1, NF_IO[6] -# bit 23-20: MPPSel5 1, NF_IO[7] -# bit 27-24: MPPSel6 1, SYSRST_O -# bit 31-28: MPPSel7 0, GPO[7]
-DATA 0xFFD10004 0x03303300
-DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: MPPSel16 0, GPIO[16] -# bit 7-4: MPPSel17 0, GPIO[17] -# bit 12-8: MPPSel18 1, NF_IO[0] -# bit 15-12: MPPSel19 1, NF_IO[1] -# bit 19-16: MPPSel20 0, GPIO[20] -# bit 23-20: MPPSel21 0, GPIO[21] -# bit 27-24: MPPSel22 0, GPIO[22] -# bit 31-28: MPPSel23 0, GPIO[23]
-DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
-# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
-#Dram initalization -DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register -# bit13-0: 0x400 (DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01
-DATA 0xFFD01404 0x39543000 # DDR Controller Control Low -# bit 3-0: 0 reserved -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay
-DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP
-DATA 0xFFD0140C 0x00000033 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required
-DATA 0xFFD01410 0x0000000D # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required
-DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required
-DATA 0xFFD0141C 0x00000652 # DDR Mode -DATA 0xFFD01420 0x00000044 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 1, DDR ODT control lsd disabled -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, enabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required
-DATA 0xFFD01424 0x0000F07F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 0 , no sample stage -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required -DATA 0xFFD01428 0x00074510 -DATA 0xFFD0147c 0x00007451
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x07, Size (i.e. 128MB)
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) -# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0 -# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 00, ODT1 controlled by register -# bit31-4: zero, required
-DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control -# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0 -# bit9-8: 1, ODTEn, never active -# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit0=1, enable DDR init upon this register write
-# End of Header extension -DATA 0x0 0x0 diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg deleted file mode 100644 index e30c0fe..0000000 --- a/board/keymile/km_arm/kwbimage_128M16_1.cfg +++ /dev/null @@ -1,257 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2010 -# Heiko Schocher, DENX Software Engineering, hs@denx.de. -# -# (C) Copyright 2012 -# Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com -# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com -# -# (C) Copyright 2012 -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -#
-# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash
-DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) -# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) -# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) -# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) -# bit 19-16: 1, MPPSel4 NF_IO[6] -# bit 23-20: 1, MPPSel5 NF_IO[7] -# bit 27-24: 1, MPPSel6 SYSRST_O -# bit 31-28: 0, MPPSel7 GPO[7]
-DATA 0xFFD10004 0x03303300 # MPP Control 1 Register -# bit 3-0: 0, MPPSel8 GPIO[8] -# bit 7-4: 0, MPPSel9 GPIO[9] -# bit 12-8: 3, MPPSel10 UA0_TXD -# bit 15-12: 3, MPPSel11 UA0_RXD -# bit 19-16: 0, MPPSel12 not connected -# bit 23-20: 3, MPPSel13 UA1_TXD -# bit 27-24: 3, MPPSel14 UA1_RXD -# bit 31-28: 0, MPPSel15 GPIO[15]
-DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: 0, MPPSel16 GPIO[16] -# bit 7-4: 0, MPPSel17 not connected -# bit 12-8: 1, MPPSel18 NF_IO[0] -# bit 15-12: 1, MPPSel19 NF_IO[1] -# bit 19-16: 0, MPPSel20 GPIO[20] -# bit 23-20: 0, MPPSel21 GPIO[21] -# bit 27-24: 0, MPPSel22 GPIO[22] -# bit 31-28: 0, MPPSel23 GPIO[23]
-# MPP Control 3-6 Register untouched (MPP24-49)
-DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -# bit 2-0: 3, Reserved -# bit 5-3: 3, Reserved -# bit 6: 0, Reserved -# bit 7: 0, RGMII-pads voltage = 3.3V -# bit 10-8: 3, Reserved -# bit 13-11: 3, Reserved -# bit 14: 0, Reserved -# bit 15: 0, MPP RGMII-pads voltage = 3.3V -# bit 31-16 0x1B1B, Reserved
-DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -# bit 0-1: 2, Tag RAM RTC RAM0 -# bit 3-2: 1, Tag RAM WTC RAM0 -# bit 7-4: 6, Reserve -# bit 9-8: 2, Valid RAM RTC RAM -# bit 11-10: 1, Valid RAM WTC RAM -# bit 13-12: 2, Dirty RAM RTC RAM -# bit 15-14: 1, Dirty RAM WTC RAM -# bit 17-16: 2, Data RAM RTC RAM0 -# bit 19-18: 1, Data RAM WTC RAM0 -# bit 21-20: 2, Data RAM RTC RAM1 -# bit 23-22: 1, Data RAM WTC RAM1 -# bit 25-24: 2, Data RAM RTC RAM2 -# bit 27-26: 1, Data RAM WTC RAM2 -# bit 29-28: 2, Data RAM RTC RAM3 -# bit 31-30: 1, Data RAM WTC RAM4
-DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -# bit 15-0: ???, Reserve -# bit 17-16: 2, ECC RAM RTC RAM0 -# bit 19-18: 1, ECC RAM WTC RAM0 -# bit 31-20: ???,Reserve
-# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
-# SDRAM initalization -DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register -# bit 13-0: 0x4E0, DDR2 clks refresh rate -# bit 14: 0, reserved -# bit 15: 0, reserved -# bit 16: 0, CPU to Dram Write buffer policy -# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic -# bit 19-18: 0, reserved -# bit 23-20: 0, reserved -# bit 24: 1, enable exit self refresh mode on DDR access -# bit 25: 1, required -# bit 29-26: 0, reserved -# bit 31-30: 1, reserved
-DATA 0xFFD01404 0x36543000 # DDR Controller Control Low -# bit 3-0: 0, reserved -# bit 4: 0, 2T mode =addr/cmd in same cycle -# bit 5: 0, clk is driven during self refresh, we don't care for APX -# bit 6: 0, use recommended falling edge of clk for addr/cmd -# bit 7-11: 0, reserved -# bit 12-13: 1, reserved, required 1 -# bit 14: 0, input buffer always powered up -# bit 17-15: 0, reserved -# bit 18: 1, cpu lock transaction enabled -# bit 19: 0, reserved -# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 -# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM -# bit 30-28: 3, required -# bit 31: 0,no additional STARTBURST delay
-DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) -# bit 3-0: 0xE, TRAS, 15 clk (45 ns) -# bit 7-4: 0x4, TRCD, 5 clk (15 ns) -# bit 11-8: 0x4, TRP, 5 clk (15 ns) -# bit 15-12: 0x4, TWR, 5 clk (15 ns) -# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) -# bit 20: 0, extended TRAS msb -# bit 23-21: 0, reserved -# bit 27-24: 0x3, TRRD, 4 clk (10 ns) -# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns)
-DATA 0xFFD0140C 0x0000003e # DDR Timing (High) -# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) -# bit 8-7: 0, TR2R -# bit 10-9: 0, TR2W -# bit 12-11: 0, TW2W -# bit 31-13: 0, reserved
-DATA 0xFFD01410 0x00000001 # DDR Address Control -# bit 1-0: 1, Cs0width=x16 -# bit 3-2: 0, Cs0size=2Gb -# bit 5-4: 0, Cs1width=nonexistent -# bit 7-6: 0, Cs1size =nonexistent -# bit 9-8: 0, Cs2width=nonexistent -# bit 11-10: 0, Cs2size =nonexistent -# bit 13-12: 0, Cs3width=nonexistent -# bit 15-14: 0, Cs3size =nonexistent -# bit 16: 0, Cs0AddrSel -# bit 17: 0, Cs1AddrSel -# bit 18: 0, Cs2AddrSel -# bit 19: 0, Cs3AddrSel -# bit 31-20: 0, required
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit 0: 0, OpenPage enabled -# bit 31-1: 0, required
-DATA 0xFFD01418 0x00000000 # DDR Operation -# bit 3-0: 0, DDR cmd -# bit 31-4: 0, required
-DATA 0xFFD0141C 0x00000652 # DDR Mode -# bit 2-0: 2, Burst Length = 4 -# bit 3: 0, Burst Type -# bit 6-4: 5, CAS Latency = 5 -# bit 7: 0, Test mode -# bit 8: 0, DLL Reset -# bit 11-9: 3, Write recovery for auto-precharge must be 3 -# bit 12: 0, Active power down exit time, fast exit -# bit 14-13: 0, reserved -# bit 31-15: 0, reserved
-DATA 0xFFD01420 0x00000006 # DDR Extended Mode -# bit 0: 0, DDR DLL enabled -# bit 1: 1, DDR drive strength reduced -# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] -# bit 5-3: 0, required -# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] -# bit 9-7: 0, required -# bit 10: 0, differential DQS enabled -# bit 11: 0, required -# bit 12: 0, DDR output buffer enabled -# bit 31-13: 0 required
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit 2-0: 7, required -# bit 3: 1, MBUS Burst Chop disabled -# bit 6-4: 7, required -# bit 7: 0, reserved -# bit 8: 1, add sample stage required for f > 266 MHz -# bit 9: 0, no half clock cycle addition to dataout -# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals -# bit 11: 0, 1/4 clock cycle skew disabled for write mesh -# bit 15-12:0xf, required -# bit 31-16: 0, required
-DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low -# bit 3-0: 0, required -# bit 7-4: 2, M_ODT assertion 2 cycles after read start command -# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command -# (ODT turn off delay 2,5 clk cycles) -# bit 15-12: 4, internal ODT time based on bit 7-4 -# with the considered SDRAM internal delay -# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 -# with the considered SDRAM internal delay -# bit 31-20: 0, required
-DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High -# bit 3-0: 2, M_ODT assertion same as bit 11-8 -# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 -# bit 11-8: 4, internal ODT assertion 2 cycles after write start command -# with the considered SDRAM internal delay -# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command -# with the considered SDRAM internal delay
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -# bit 23-0: 0, reserved -# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
-DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit 0: 1, Window enabled -# bit 1: 0, Write Protect disabled -# bit 3-2: 0, CS0 hit selected -# bit 23-4:ones, required -# bit 31-24: 0x0F, Size (i.e. 256MB)
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 -# bit 7-4: 0, ODT0Rd, MODT[1] not asserted -# bit 11-8: 0, required -# big 15-11: 0, required -# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 -# bit 23-20: 0, ODT0Wr, MODT[1] not asserted -# bit 27-24: 0, required -# bit 31-28: 0, required
-DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above -# bit 3-2: 0, ODT1 controlled by register -# bit 31-4: 0, required
-DATA 0xFFD0149C 0x0000E801 # CPU ODT Control -# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 -# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM -# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr -# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm -# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm -# bit 14: 1, STARTBURST ODT enabled -# bit 15: 1, Use ODT Block
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit 0: 1, enable DDR init upon this register write -# bit 31-1: 0, reserved
-# End of Header extension -DATA 0x0 0x0 diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg deleted file mode 100644 index 91ea5f0..0000000 --- a/board/keymile/km_arm/kwbimage_256M8_1.cfg +++ /dev/null @@ -1,257 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2012 -# Stefan Bigler, Keymile AG, stefan.bigler@keymile.com -# Norbert Mayer, Keymile AG, norbert.mayer@keymile.com -# Deepak Patel, XENTECH Limited, deepak.patel@xentech.co.uk -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# -# This configuration applies to COGE5 design (ARM-part) -# Two 8-Bit devices are connected on the 16-Bit bus on the same -# chip-select. The supported devices are -# MT47H256M8EB-3IT:C -# MT47H256M8EB-25EIT:C
-# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash
-DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) -# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) -# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) -# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) -# bit 19-16: 1, MPPSel4 NF_IO[6] -# bit 23-20: 1, MPPSel5 NF_IO[7] -# bit 27-24: 1, MPPSel6 SYSRST_O -# bit 31-28: 0, MPPSel7 GPO[7]
-DATA 0xFFD10004 0x03303300 # MPP Control 1 Register -# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged -# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged -# bit 12-8: 3, MPPSel10 UA0_TXD -# bit 15-12: 3, MPPSel11 UA0_RXD -# bit 19-16: 0, MPPSel12 not connected -# bit 23-20: 3, MPPSel13 GPIO[14] -# bit 27-24: 3, MPPSel14 GPIO[15] -# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal)
-DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: 0, MPPSel16 GPIO[16] -# bit 7-4: 0, MPPSel17 not connected -# bit 11-8: 1, MPPSel18 NF_IO[0] -# bit 15-12: 1, MPPSel19 NF_IO[1] -# bit 19-16: 0, MPPSel20 GPIO[20] -# bit 23-20: 0, MPPSel21 GPIO[21] -# bit 27-24: 0, MPPSel22 GPIO[22] -# bit 31-28: 0, MPPSel23 GPIO[23]
-# MPP Control 3-6 Register untouched (MPP24-49)
-DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -# bit 2-0: 3, Reserved -# bit 5-3: 3, Reserved -# bit 6: 0, Reserved -# bit 7: 0, RGMII-pads voltage = 3.3V -# bit 10-8: 3, Reserved -# bit 13-11: 3, Reserved -# bit 14: 0, Reserved -# bit 15: 0, MPP RGMII-pads voltage = 3.3V -# bit 31-16 0x1B1B, Reserved
-DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -# bit 0-1: 2, Tag RAM RTC RAM0 -# bit 3-2: 1, Tag RAM WTC RAM0 -# bit 7-4: 6, Reserved -# bit 9-8: 2, Valid RAM RTC RAM -# bit 11-10: 1, Valid RAM WTC RAM -# bit 13-12: 2, Dirty RAM RTC RAM -# bit 15-14: 1, Dirty RAM WTC RAM -# bit 17-16: 2, Data RAM RTC RAM0 -# bit 19-18: 1, Data RAM WTC RAM0 -# bit 21-20: 2, Data RAM RTC RAM1 -# bit 23-22: 1, Data RAM WTC RAM1 -# bit 25-24: 2, Data RAM RTC RAM2 -# bit 27-26: 1, Data RAM WTC RAM2 -# bit 29-28: 2, Data RAM RTC RAM3 -# bit 31-30: 1, Data RAM WTC RAM4
-DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -# bit 15-0: ?, Reserved -# bit 17-16: 2, ECC RAM RTC RAM0 -# bit 19-18: 1, ECC RAM WTC RAM0 -# bit 31-20: ?,Reserved
-# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
-# SDRAM initalization -DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register -# bit 13-0: 0x4E0, DDR2 clks refresh rate -# bit 14: 0, reserved -# bit 15: 0, reserved -# bit 16: 0, CPU to Dram Write buffer policy -# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic -# bit 19-18: 0, reserved -# bit 23-20: 0, reserved -# bit 24: 1, enable exit self refresh mode on DDR access -# bit 25: 1, required -# bit 29-26: 0, reserved -# bit 31-30: 1, reserved
-DATA 0xFFD01404 0x36543000 # DDR Controller Control Low -# bit 3-0: 0, reserved -# bit 4: 0, 2T mode =addr/cmd in same cycle -# bit 5: 0, clk is driven during self refresh, we don't care for APX -# bit 6: 0, use recommended falling edge of clk for addr/cmd -# bit 7-11: 0, reserved -# bit 12-13: 1, reserved, required 1 -# bit 14: 0, input buffer always powered up -# bit 17-15: 0, reserved -# bit 18: 1, cpu lock transaction enabled -# bit 19: 0, reserved -# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 -# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM -# bit 30-28: 3, required -# bit 31: 0, no additional STARTBURST delay
-DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) -# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles -# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles -# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles -# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles -# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles -# bit 20: 0, extended TRAS msb -# bit 23-21: 0, reserved -# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles -# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles
-DATA 0xFFD0140C 0x0000003E # DDR Timing (High) -# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles -# bit 8-7: 0, TR2R -# bit 10-9: 0, TR2W -# bit 12-11: 0, TW2W -# bit 31-13: 0, reserved
-DATA 0xFFD01410 0x00000000 # DDR Address Control -# bit 1-0: 0, Cs0width=x8 (2 devices) -# bit 3-2: 0, Cs0size=2Gb -# bit 5-4: 0, Cs1width=nonexistent -# bit 7-6: 0, Cs1size =nonexistent -# bit 9-8: 0, Cs2width=nonexistent -# bit 11-10: 0, Cs2size =nonexistent -# bit 13-12: 0, Cs3width=nonexistent -# bit 15-14: 0, Cs3size =nonexistent -# bit 16: 0, Cs0AddrSel -# bit 17: 0, Cs1AddrSel -# bit 18: 0, Cs2AddrSel -# bit 19: 0, Cs3AddrSel -# bit 31-20: 0, required
-DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit 0: 0, OpenPage enabled -# bit 31-1: 0, required
-DATA 0xFFD01418 0x00000000 # DDR Operation -# bit 3-0: 0, DDR cmd -# bit 31-4: 0, required
-DATA 0xFFD0141C 0x00000652 # DDR Mode -# bit 2-0: 2, Burst Length = 4 -# bit 3: 0, Burst Type -# bit 6-4: 5, CAS Latency = 5 -# bit 7: 0, Test mode -# bit 8: 0, DLL Reset -# bit 11-9: 3, Write recovery for auto-precharge must be 3 -# bit 12: 0, Active power down exit time, fast exit -# bit 14-13: 0, reserved -# bit 31-15: 0, reserved
-DATA 0xFFD01420 0x00000006 # DDR Extended Mode -# bit 0: 0, DDR DLL enabled -# bit 1: 1, DDR drive strenght reduced -# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] -# bit 5-3: 0, required -# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] -# bit 9-7: 0, required -# bit 10: 0, differential DQS enabled -# bit 11: 0, required -# bit 12: 0, DDR output buffer enabled -# bit 31-13: 0 required
-DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit 2-0: 7, required -# bit 3: 1, MBUS Burst Chop disabled -# bit 6-4: 7, required -# bit 7: 0, reserved -# bit 8: 1, add sample stage required for > 266Mhz -# bit 9: 0, no half clock cycle addition to dataout -# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals -# bit 11: 0, 1/4 clock cycle skew disabled for write mesh -# bit 15-12:0xf, required -# bit 31-16: 0, required
-DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low -# bit 3-0: 0, required -# bit 7-4: 2, M_ODT assertion 2 cycles after read start command -# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command -# (ODT turn off delay 2,5 clk cycles) -# bit 15-12: 4, internal ODT time based on bit 7-4 -# with the considered SDRAM internal delay -# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 -# with the considered SDRAM internal delay -# bit 31-20: 0, required
-DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High -# bit 3-0: 2, M_ODT assertion same as bit 11-8 -# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 -# bit 11-8: 4, internal ODT assertion 2 cycles after write start command -# with the considered SDRAM internal delay -# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command -# with the considered SDRAM internal delay
-DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -# bit 23-0: 0, reserved -# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24]
-DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size -# bit 0: 1, Window enabled -# bit 1: 0, Write Protect disabled -# bit 3-2: 0, CS0 hit selected -# bit 23-4:ones, required -# bit 31-24:0x1F, Size (i.e. 512MB)
-DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
-DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 -# bit 7-4: 0, ODT0Rd, MODT[1] not asserted -# bit 11-8: 0, required -# big 15-11: 0, required -# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 -# bit 23-20: 0, ODT0Wr, MODT[1] not asserted -# bit 27-24: 0, required -# bit 31-28: 0, required
-DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) -# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above -# bit 3-2: 1, ODT1 never active -# bit 31-4: 0, required
-DATA 0xFFD0149C 0x0000E801 # CPU ODT Control -# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 -# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr -# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm -# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm -# bit 14: 1, STARTBURST ODT enabled -# bit 15: 1, Use ODT Block
-DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit 0: 1, enable DDR init upon this register write -# bit 31-1: 0, reserved
-# End of Header extension -DATA 0x0 0x0 diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt index 4384c0d..1bdff2f 100644 --- a/board/keymile/scripts/develop-common.txt +++ b/board/keymile/scripts/develop-common.txt @@ -8,5 +8,5 @@ tftpkernel=tftpboot ${load_addr_r} ${tftppath}/${uimage} toolchain=/opt/eldk rootfssize=0 set_uimage=printenv uimage || setenv uimage uImage -set_tftppath=if test ${hostname} = kmcoge5un; then setenv tftppath CI5UN; else if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi; fi +set_tftppath=if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi try_import_nfs_path=if tftpboot ${load_addr_r} ${tftppath}/nfs-path.txt; then env import -t ${load_addr_r} ${filesize}; else echo no auto nfs path imported; echo you can set nfsargs in /tftpboot/${tftppath}/nfs-path.txt and rerun develop; fi diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig deleted file mode 100644 index 054038f..0000000 --- a/configs/km_kirkwood_128m16_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -# CONFIG_KIRKWOOD_PCIE_INIT is not set -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood 128M16" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_KM_KIRKWOOD_128M16=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig deleted file mode 100644 index ac2deeb..0000000 --- a/configs/km_kirkwood_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -# CONFIG_KIRKWOOD_PCIE_INIT is not set -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_KM_KIRKWOOD=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig deleted file mode 100644 index 8074679..0000000 --- a/configs/km_kirkwood_pci_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood PCI" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_KM_FPGA_CONFIG=y -CONFIG_KM_KIRKWOOD_PCI=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig deleted file mode 100644 index 5766f49..0000000 --- a/configs/kmcoge5un_defconfig +++ /dev/null @@ -1,84 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_256M8_1.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -# CONFIG_KIRKWOOD_PCIE_INIT is not set -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0xD0000 -CONFIG_IDENT_STRING="\nHitachi Power Grids COGE5UN" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 -CONFIG_KM_ENV_IS_IN_SPI_NOR=y -CONFIG_KM_PIGGY4_88E6352=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig deleted file mode 100644 index a309aca..0000000 --- a/configs/kmnusa_defconfig +++ /dev/null @@ -1,85 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0xD0000 -CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_KM_FPGA_CONFIG=y -CONFIG_KM_ENV_IS_IN_SPI_NOR=y -CONFIG_KM_PIGGY4_88E6352=y -CONFIG_KM_NUSA=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MV88E6352_SWITCH=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/configs/kmsuse2_defconfig b/configs/kmsuse2_defconfig deleted file mode 100644 index de44deb..0000000 --- a/configs/kmsuse2_defconfig +++ /dev/null @@ -1,85 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0xD0000 -CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_KM_FPGA_CONFIG=y -CONFIG_KM_FPGA_FORCE_CONFIG=y -CONFIG_KM_FPGA_NO_RESET=y -CONFIG_KM_ENV_IS_IN_SPI_NOR=y -CONFIG_KM_SUSE2=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h deleted file mode 100644 index a91e5e8..0000000 --- a/include/configs/km/km_arm.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Prafulla Wadaskar prafulla@marvell.com
- (C) Copyright 2009
- Stefan Roese, DENX Software Engineering, sr@denx.de.
- (C) Copyright 2010-2011
- Heiko Schocher, DENX Software Engineering, hs@denx.de.
- */
-/*
- for linking errors see
- */
-#ifndef _CONFIG_KM_ARM_H -#define _CONFIG_KM_ARM_H
-#define CONFIG_NAND_ECC_BCH
-/* include common defines/options for all Keymile boards */ -#include "keymile-common.h"
-/* Increase max size of compressed kernel */
-#include "asm/arch/config.h"
-/* architecture specific default bootargs */ -#define CONFIG_KM_DEF_BOOT_ARGS_CPU \
"bootcountaddr=${bootcountaddr} ${mtdparts}" \" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"-#define CONFIG_KM_DEF_ENV_CPU \
- "u-boot=" CONFIG_HOSTNAME "/u-boot.kwb\0" \
- CONFIG_KM_UPDATE_UBOOT \
- "set_fdthigh=setenv fdt_high ${kernelmem}\0" \
- "checkfdt=" \
"if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; " \"then true; else setenv cramfsloadfdt true; " \"setenv boot bootm ${load_addr_r}; " \"echo No FDT found, booting with the kernel " \"appended one; fi\0" \- ""
-/*
- NAND Flash configuration
- */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-/*
- Other required minimal configurations
- */
-/*
- Ethernet Driver configuration
- */
-#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer autoneg timeout */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0
-/*
- I2C related stuff
- */
-#undef CONFIG_I2C_MVTWSI -#define CONFIG_SYS_I2C_INIT_BOARD
-#define CONFIG_SYS_NUM_I2C_BUSES 6 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \{0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \{0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \{0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \}-#ifndef __ASSEMBLY__ -#include <asm/arch/gpio.h> -#include <linux/delay.h> -#include <linux/stringify.h> -extern void __set_direction(unsigned pin, int high); -#define KM_KIRKWOOD_SDA_PIN 8 -#define KM_KIRKWOOD_SCL_PIN 9 -#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 -#define KM_KIRKWOOD_ENV_WP 38
-#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0) -#define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1) -#define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0) -#define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit) -#define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit) -#endif
-#define I2C_DELAY udelay(1) -#define I2C_SOFT_DECLARATIONS
-/*
- Environment variables configurations
- */
-#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR -#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ -#else -#define CONFIG_SYS_EEPROM_WREN -#define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */ -#endif
-#define KM_FLASH_GPIO_PIN 16
-#define CONFIG_KM_UPDATE_UBOOT \
- "update=" \
"sf probe 0;sf erase 0 +${filesize};" \"sf write ${load_addr_r} 0 ${filesize};\0"-#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR -#define CONFIG_KM_NEW_ENV \
- "newenv=sf probe 0;" \
"sf erase " __stringify(CONFIG_ENV_OFFSET) " " \__stringify(CONFIG_ENV_TOTAL_SIZE)"\0"-#else -#define CONFIG_KM_NEW_ENV \
- "newenv=setenv addr 0x100000 && " \
"i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \"mw.b ${addr} 0 4 && " \"eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \" ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \"eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"-#endif
-#ifndef CONFIG_KM_BOARD_EXTRA_ENV -#define CONFIG_KM_BOARD_EXTRA_ENV "" -#endif
-/*
- Default environment variables
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- CONFIG_KM_BOARD_EXTRA_ENV \
- CONFIG_KM_DEF_ENV \
- CONFIG_KM_NEW_ENV \
- "arch=arm\0" \
- ""
-/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000
-/* address for the bootcount (taken from end of RAM) */ -#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM)
-/* enable POST tests */ -#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) -#define CONFIG_POST_SKIP_ENV_FLAGS -#define CONFIG_POST_EXTERNAL_WORD_FUNCS
-#endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h deleted file mode 100644 index 01482d5..0000000 --- a/include/configs/km_kirkwood.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*
- (C) Copyright 2009
- Marvell Semiconductor <www.marvell.com>
- Prafulla Wadaskar prafulla@marvell.com
- (C) Copyright 2009
- Stefan Roese, DENX Software Engineering, sr@denx.de.
- (C) Copyright 2011-2012
- Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
- Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
- */
-/*
- for linking errors see
- */
-#ifndef _CONFIG_KM_KIRKWOOD_H -#define _CONFIG_KM_KIRKWOOD_H
-/* KM_KIRKWOOD */ -#if defined(CONFIG_KM_KIRKWOOD) -#define CONFIG_HOSTNAME "km_kirkwood"
-/* KM_KIRKWOOD_PCI */ -#elif defined(CONFIG_KM_KIRKWOOD_PCI) -#define CONFIG_HOSTNAME "km_kirkwood_pci" -#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
-/* KM_KIRKWOOD_128M16 */ -#elif defined(CONFIG_KM_KIRKWOOD_128M16) -#define CONFIG_HOSTNAME "km_kirkwood_128m16"
-/* KM_NUSA */ -#elif defined(CONFIG_KM_NUSA)
-#define CONFIG_HOSTNAME "kmnusa"
-/* KMCOGE5UN */ -#elif defined(CONFIG_KM_COGE5UN) -#define CONFIG_HOSTNAME "kmcoge5un"
-/* KM_SUSE2 */ -#elif defined(CONFIG_KM_SUSE2) -#define CONFIG_HOSTNAME "kmsuse2" -#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE -#else -#error ("Board unsupported") -#endif
-/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h"
-#if defined(CONFIG_KM_PIGGY4_88E6352) -/*
- Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
- an Marvell 88E6352 simple switch.
- In this case we have to change the default settings for the etherent mac.
- There is NO ethernet phy. The ARM and Switch are conencted directly over
- RGMII in MAC-MAC mode
- In this case 1GBit full duplex and autoneg off
- */
-#define PORT_SERIAL_CONTROL_VALUE ( \
- MVGBE_FORCE_LINK_PASS | \
- MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
- MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
- MVGBE_ADV_NO_FLOW_CTRL | \
- MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- MVGBE_FORCE_BP_MODE_NO_JAM | \
- (1 << 9) /* Reserved bit has to be 1 */ | \
- MVGBE_DO_NOT_FORCE_LINK_FAIL | \
- MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
- MVGBE_DTE_ADV_0 | \
- MVGBE_MIIPHY_MAC_MODE | \
- MVGBE_AUTO_NEG_NO_CHANGE | \
- MVGBE_MAX_RX_PACKET_1552BYTE | \
- MVGBE_CLR_EXT_LOOPBACK | \
- MVGBE_SET_FULL_DUPLEX_MODE | \
- MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
- MVGBE_SET_GMII_SPEED_TO_1000 |\
- MVGBE_SET_MII_SPEED_TO_100)
-#endif
-#ifdef CONFIG_KM_PIGGY4_88E6061 -/*
- Some keymile boards like mgcoge5un have their PIGGY4 connected via
- an Marvell 88E6061 simple switch.
- In this case we have to change the default settings for the
- ethernet phy connected to the kirkwood.
- In this case 100MB full duplex and autoneg off
- */
-#define PORT_SERIAL_CONTROL_VALUE ( \
- MVGBE_FORCE_LINK_PASS | \
- MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
- MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
- MVGBE_ADV_NO_FLOW_CTRL | \
- MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
- MVGBE_FORCE_BP_MODE_NO_JAM | \
- (1 << 9) /* Reserved bit has to be 1 */ | \
- MVGBE_DO_NOT_FORCE_LINK_FAIL | \
- MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
- MVGBE_DTE_ADV_0 | \
- MVGBE_MIIPHY_MAC_MODE | \
- MVGBE_AUTO_NEG_NO_CHANGE | \
- MVGBE_MAX_RX_PACKET_1552BYTE | \
- MVGBE_CLR_EXT_LOOPBACK | \
- MVGBE_SET_FULL_DUPLEX_MODE | \
- MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
- MVGBE_SET_GMII_SPEED_TO_10_100 |\
- MVGBE_SET_MII_SPEED_TO_100)
-#endif
-#endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 4f628e0..648b91e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -238,7 +238,6 @@ CONFIG_IRAM_BASE CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_IRAM_TOP -CONFIG_KM_BOARD_EXTRA_ENV CONFIG_KM_DEF_ARCH CONFIG_KM_DEF_BOOT_ARGS_CPU CONFIG_KM_DEF_ENV
Viele Grüße, Stefan Roese