Hi Bin, Jagan,
Thanks Jagan for posting the patches to enable QUAD SPI-NOR on HiFive Unleashed along with other sequels.
-----Original Message----- From: Bin Meng bmeng.cn@gmail.com Sent: Tuesday, April 21, 2020 4:44 AM To: Jagan Teki jagan@amarulasolutions.com Cc: Vignesh R vigneshr@ti.com; U-Boot Mailing List <u- boot@lists.denx.de>; Suneel Garapati suneelglinux@gmail.com; Sagar Kadam sagar.kadam@sifive.com; Bhargav Shah bhargavshah1988@gmail.com; Simon Glass sjg@chromium.org; Tom Rini trini@konsulko.com; linux-amarula <linux- amarula@amarulasolutions.com> Subject: Re: [PATCH 3/3] spi: sifive: Fix format register proto field
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On Mon, Apr 20, 2020 at 8:09 PM Jagan Teki jagan@amarulasolutions.com wrote:
SiFive SPI controller has a proto bit field in frame format register which would be used to configure the SPI I/O protocol lines used on specific transfer.
Right now the driver is configuring this proto using slave->mode which is used for data transfer and opcode, address vary depending on the particular transfer at runtime.
Now the SPI framework supports per transfer I/O protocol lines, so use spi->proto instead of slave-mode.
Signed-off-by: Jagan Teki jagan@amarulasolutions.com
drivers/spi/spi-sifive.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-)
This patch does not apply on top of u-boot/master.
Please rebase and resend.
I guess Bin, you will also have to add following two patch series [1] and [2] before this set. I tested this and other series with following dependency chain over u-boot/master(e4837da7828293ea49abc579f939c0f5c4b127c3)
1> 1-2-mtd-spi-nor-Enable-QE-bit-for-ISSI-flash.patch 2> spi-sifive-Tidy-up-dm_spi_slave_platdata-variable.patch 3> spi: Support SPI I/O protocol lines 4> riscv: sifive/fu540: Enable SPI-NOR support
I could verify flash erase/read/write operations along with mmc spi.
[1] https://patchwork.ozlabs.org/project/uboot/patch/20200420100607.23009-1-jaga... [2] https://patchwork.amarulasolutions.com/patch/1083/
Thanks & BR, Sagar Kadam
Regards, Bin