Hi Stefano,
+DECLARE_GLOBAL_DATA_PTR;
+__weak void ddr_init(void) +{ +};
This weak could be dropped, it was surely for test purpose :-)
I understand patch 23/23 about the ddr script, it is hard to be accepted. So I add a weak function here to avoid build failure if other 22 patches could be accepted. It may take long time to convert the ddr script to structure based.
Ok, understand.
So would you like to me to drop it and keep 23/23 in V3, or keep the weak ddr_init and drop 23/23 in V3?
Thing is that this patch is dead code without DDR setup. I am ready to merge reviewed patch, even if they add MX8M and there is not yet any board using - theoretically, this is also dead code and I could not. But this simplifies the development and you can reduce the number of patches to be posted next time.
Thanks.
But merging a board that is known to be broken due to a missing part, it is
nonsense. Board will be merged when we have a suitable way to set the DDR controller.
Ok. Understand.
Thanks, Peng.
Regards, Stefano
+void spl_dram_init(void) +{
- /* ddr init */
- ddr_init();
+}
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) struct i2c_pads_info +i2c_pad_info1 = {
- .scl = {
.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,.gp = IMX_GPIO_NR(5, 14),- },
- .sda = {
.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,.gp = IMX_GPIO_NR(5, 15),- },
+};
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) #define
USDHC2_PWR_GPIO
+IMX_GPIO_NR(2, 19)
+int board_mmc_getcd(struct mmc *mmc) {
- struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- int ret = 0;
- switch (cfg->esdhc_base) {
- case USDHC1_BASE_ADDR:
ret = 1;break;- case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);return ret;- }
- return 1;
+}
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS |
PAD_CTL_PUE | \
PAD_CTL_FSEL2)+static iomux_v3_cfg_t const usdhc1_pads[] = {
- IMX8MQ_PAD_SD1_CLK__USDHC1_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_CMD__USDHC1_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 |
MUX_PAD_CTRL(NO_PAD_CTRL), };
+static iomux_v3_cfg_t const usdhc2_pads[] = {
- IMX8MQ_PAD_SD2_CLK__USDHC2_CLK |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD2_CMD__USDHC2_CMD |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 |
MUX_PAD_CTRL(USDHC_PAD_CTRL),
- IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 |
MUX_PAD_CTRL(NO_PAD_CTRL),
- IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 |
MUX_PAD_CTRL(NO_PAD_CTRL), };
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
- {USDHC1_BASE_ADDR, 0, 8},
- {USDHC2_BASE_ADDR, 0, 4},
+};
+int board_mmc_init(bd_t *bis) +{
- int i, ret;
- /*
* According to the board_mmc_init() the following map is done:* (U-Boot device node) (Physical Port)* mmc0 USDHC1* mmc1 USDHC2*/- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {case 0:init_clk_usdhc(0);usdhc_cfg[0].sdhc_clk =mxc_get_clock(USDHC1_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");gpio_direction_output(USDHC1_PWR_GPIO, 0);udelay(500);gpio_direction_output(USDHC1_PWR_GPIO, 1);break;case 1:init_clk_usdhc(1);usdhc_cfg[1].sdhc_clk =mxc_get_clock(USDHC2_CLK_ROOT);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");gpio_direction_output(USDHC2_PWR_GPIO, 0);udelay(500);gpio_direction_output(USDHC2_PWR_GPIO, 1);break;default:printf("Warning: you configured more USDHCcontrollers(%d) than supported by the board\n", i + 1);
return -EINVAL;}ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);if (ret)return ret;- }
- return 0;
+}
+#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{
- struct pmic *p;
- int ret;
- unsigned int reg;
- ret = power_pfuze100_init(I2C_PMIC);
- if (ret)
return -ENODEV;- p = pmic_get("PFUZE100");
- ret = pmic_probe(p);
- if (ret)
return -ENODEV;- pmic_reg_read(p, PFUZE100_DEVICEID, ®);
- printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
- pmic_reg_read(p, PFUZE100_SW3AVOL, ®);
- if ((reg & 0x3f) != 0x18) {
reg &= ~0x3f;reg |= 0x18;pmic_reg_write(p, PFUZE100_SW3AVOL, reg);- }
- ret = pfuze_mode_init(p, APS_PFM);
- if (ret < 0)
return ret;- return 0;
+} +#endif
+void spl_board_init(void) +{
- enable_tzc380();
Just for my understanding: is this board specific ? Enabling the TrustZone controller looks to me more general, but I am maybe wrong. Can you better explain me this ? Thanks !
If want to use TZC380 on i.MX, TZC380 needs to be enabled before DDR initialization. So I put it in spl_board_init.
TZC380 enablement is not a must for all boards.
We will enable TEE on i.MX8MQ EVK board, so need to enable TZC380.
Thanks, Peng
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