Erratum A008514 workround requires writing register eddrtqcr1 with value 0x63b20002.
Signed-off-by: York Sun yorksun@freescale.com ---
drivers/ddr/fsl/fsl_ddr_gen4.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 480f384..f44c155 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -32,21 +32,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 temp_sdram_cfg; u32 total_gb_size_per_controller; int timeout; -#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008514) u32 *eddrtqcr1; #endif
switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; -#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008514) eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; #endif break; #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) case 1: ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; -#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008514) eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; #endif break; @@ -54,7 +57,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) case 2: ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; -#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008514) eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; #endif break; @@ -62,7 +66,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) case 3: ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; -#ifdef CONFIG_SYS_FSL_ERRATUM_A008336 +#if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \ + defined(CONFIG_SYS_FSL_ERRATUM_A008514) eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800; #endif break; @@ -82,6 +87,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #endif ddr_out32(eddrtqcr1, 0x63b30002); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A008514 +#ifdef CONFIG_LS2085A + /* A008514 only applies to DP-DDR controler */ + if (ctrl_num == 2) +#endif + ddr_out32(eddrtqcr1, 0x63b20002); +#endif if (regs->ddr_eor) ddr_out32(&ddr->eor, regs->ddr_eor);