14 Nov
2014
14 Nov
'14
10:27 p.m.
On 09/17/2014 03:27 AM, Priyanka Jain wrote:
-A_007662 states that for x1 link width, PCIe2 controller trains in Gen1 speed while configured for Gen2 speed. Workaround:Set the width to x1 and speed to Gen2 by writing to CCSR registers in PBI phase
-A_008007 states that PVR register may show random value. Workaround: Reset PVR register using DCSR space in PBI phase
Add PBI based software workaround for A_007662 and A_008007 in t104x_pbi.cfg. This is required for SPL-based bootloaders like NAND-boot, SD-boot, SPI-boot
Signed-off-by: Priyanka Jain Priyanka.Jain@freescale.com
Applied to u-boot-mpc85xx master. Thanks.
York