Hello Andy,
We use a similar configuration on our custom board. The differences between your code and ours are :
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* Reference clock 50Mhz */ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_MODE_SION | MUX_PAD_CTRL(ENET_PAD_CTRL | PAD_CTL_SRE_FAST),
/* LAN Reset */ MX6_PAD_SD3_DAT3__GPIO7_IO07 | MUX_PAD_CTRL(ENET_PAD_CTRL), };
... #ifdef CONFIG_FEC_MXC
int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) phydev->drv->config(phydev); return 0; }
int board_eth_init(bd_t *bis) { int ret; struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; int reg;
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); /* Reset the PHY */ gpio_direction_output(GPIO_ENET_PHY_RESET, 0);
/* Select ENET CLK source */ reg = readl(&iomux->gpr[1]); reg |= IOMUXC_GPR1_ENET_CLK_SEL; writel(reg, &iomux->gpr[1]);
/* Configure and Start the ENET PLL */ /* diviseur => 50 MHz */ writel (BM_ANADIG_PLL_ENET_DIV_SELECT, &anatop->pll_enet_clr); writel (0x1, &anatop->pll_enet_set);
/* clear bypass et powerdown */ writel (BM_ANADIG_PLL_ENET_BYPASS | BM_ANADIG_PLL_ENET_POWERDOWN, &anatop->pll_enet_clr); /* enable */ writel (BM_ANADIG_PLL_ENET_ENABLE, &anatop->pll_enet_set);
/* Release PHY reset at least 30ms after the clock setup */ mdelay (30); gpio_set_value(GPIO_ENET_PHY_RESET, 1);
ret = cpu_eth_init(bis); if (ret) printf("FEC MXC: %s:failed\n", __func__);
return ret; } #endif
The FEC is working on our board. I hope it helps Best regards
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