On Saturday 22 December 2007, Larry Johnson wrote:
This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM controller. It should also work on the 440GRx. It is based on the DDR2 SPD code for the 440EP/440EPx, but makes no provision for DDR1 support.
This code has been tested on prototype Korat boards with three Kingston DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC (two ranks). The Korat board has a single DIMM socket, but support has been provided (though not tested) for boards with two DIMM sockets.
Signed-off-by: Larry Johnson lrj@acm.org
cpu/ppc4xx/denali_spd_ddr2.c | 1276 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 1276 insertions(+), 0 deletions(-) create mode 100644 cpu/ppc4xx/denali_spd_ddr2.c
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c new file mode 100644 index 0000000..3b50b93 --- /dev/null +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -0,0 +1,1276 @@ +/*
- cpu/ppc4xx/denali_spd_ddr2.c
- This SPD SDRAM detection code supports AMCC PPC44x CPUs with a
Denali-core + * DDR2 controller, specifically the 440EPx/GRx.
- (C) Copyright 2007
- Larry Johnson, lrj@acm.org.
- Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is...
- (C) Copyright 2007
- Stefan Roese, DENX Software Engineering, sr@denx.de.
- COPYRIGHT AMCC CORPORATION 2004
- See file CREDITS for list of people who contributed to this
- project.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
- */
+/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif
+#include <common.h> +#include <command.h> +#include <ppc4xx.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/mmu.h>
+#if defined(CONFIG_SPD_EEPROM) && \
- (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
+/*------------------------------------------------------------------------ -----+ + * Defines
*-------------------------------------------------------------------------- ---*/ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif
+#define MAXDIMMS 2 +#define MAXRANKS 2
+#define ONE_BILLION 1000000000
+#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
+#define DLL_DQS_DELAY 0x19 +#define DLL_DQS_BYPASS 0x0B +#define DQS_OUT_SHIFT 0x7F
+/*
- This DDR2 setup code can dynamically setup the TLB entries for the DDR2
memory + * region. Right now the cache should still be disabled in U-Boot because of the + * EMAC driver, that need it's buffer descriptor to be located in non cached + * memory.
- If at some time this restriction doesn't apply anymore, just define
- CFG_ENABLE_SDRAM_CACHE in the board config file and this code should
setup + * everything correctly.
- */
+#if defined(CFG_ENABLE_SDRAM_CACHE) +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ +#endif
+/*------------------------------------------------------------------------ -----+ + * Prototypes
*-------------------------------------------------------------------------- ---*/ +extern int denali_wait_for_dlllock(void); +extern void denali_core_search_data_eye(void); +extern void dcbz_area(u32 start_address, u32 num_bytes); +extern void dflush(void);
+/*
- Board-specific Platform code can reimplement spd_ddr_init_hang () if
needed + */ +void __spd_ddr_init_hang(void) +{
- hang();
+} +void spd_ddr_init_hang(void)
- __attribute__ ((weak, alias("__spd_ddr_init_hang")));
+/*
- To provide an interface for board specific config values in this common
- DDR setup code, we implement he "weak" default functions here. They
return + * the default value back to the caller.
- Please see include/configs/yucca.h for an example fora board specific
- implementation.
- */
+u32 __ddr_wrdtr(u32 default_val) +{
- return default_val;
+}
+u32 ddr_wrdtr(u32) __attribute__ ((weak, alias("__ddr_wrdtr")));
+u32 __ddr_clktr(u32 default_val) +{
- return default_val;
+}
+u32 ddr_clktr(u32) __attribute__ ((weak, alias("__ddr_clktr")));
These ddr_wrdtr() and ddr_clktr() are not used in this code. Most likely copy-and-paste from the 44x-ddr code. Please remove it.
Thanks.
Best regards, Stefan
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