Hi Fabio,
Hi Lukasz,
On Mon, Apr 1, 2019 at 11:02 AM Lukasz Majewski lukma@denx.de wrote:
After the commit: "eth: dm: fec: Add gpio phy reset binding" SHA1: efd0b791069af93e9d439a70d1fe2ae8994dbbfa
The FEC ETH driver switched to PHY GPIO reset performed with data defined in DTS. For the HSC|DDC boards the GPIO reset signal is active low and hence the wrong DTS description must be changed (otherwise the reset for ETH is not properly setup).
We should probably use the same approach as in the kernel to avoid regressions with old dtbs.
In the kernel the GPIO polarity passed in the 'phy-reset-gpios' property is ignored and it is assumed to be active low, unless 'phy-reset-active-high' is passed.
This may be a good solution.
However, I do hope that this fix will be accepted to v2019.04 as it is necessary to have ETH working (and it is the only convenient way to update u-boot on this board).
The other needed patch is to Revert "drivers/net/fec: phy_init: remove redundant logic" as pointed out by Marcel.
Thanks
Best regards,
Lukasz Majewski
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