-----Original Message----- From: York Sun [mailto:york.sun@nxp.com] Sent: Tuesday, April 19, 2016 10:03 PM To: Aneesh Bansal aneesh.bansal@nxp.com; u-boot@lists.denx.de Cc: Ruchika Gupta ruchika.gupta@nxp.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH] powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache
On 04/18/2016 05:16 AM, Aneesh Bansal wrote:
While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error checking enable) must not be changed while the L2 cache is enabled. So, L2PE must be set before enabling L2 cache.
Aneesh,
The original code set L2PE and L2E together. The L2PE bit doesn't change after that. Doesn't this satisfy the requirement? Did you observe any failure before your patch?
York
e6500 block guide states that "The value of L2PE must not be changed while the L2 cache is enabled" So, when both the bits are set together, it might lead to L2 cache getting enabled first and L2PE getting set after that. So L2PE is getting changed from 0 to 1 while L2 is still enabled which should not be done.
In normal non-secure boot, U-Boot is the first to use L2 after reset but in case of secure boot, L2 is used by Bot ROM before U-Boot. If L2PE and L2E are done together, ECC errors are observed on L2 (L2CAPTECC - L2 cache error capture ECC syndrome) and U-Boot crashes.
I believe this is because of ECC/Parity checking not getting enabled properly and resulting into erroneous detection of errors
When this is changed to setting L2PE before L2E, or not setting L2PE at all i.e. disabling ECC error checks, no ECC errors are observed and U-Boot works fine.
Aneesh