Hi Lokesh,
The following patches fix the clock parenting of couple of post-divider PLL output clocks for Main PLL0 and PLL1 on both J721E and J7200 SoCs. The Main PLL1 register values are also fixed up (they were pointing to PLL0 atm).
These PLL POSTDIV clocks are in sequence and the last POSTDIV clock acts as input clock for certain HSDIV output clocks. So, the fixes only correct the parents and their rates, and none of the child clock rates are affected.
Boot tested and verified the clock rates on both J721E and J7200 EVMs.
regards Suman
Suman Anna (2): arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks
arch/arm/mach-k3/j7200/clk-data.c | 8 ++++---- arch/arm/mach-k3/j721e/clk-data.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-)