Re: [U-Boot] [RFC] [UBOOT] [PATCH v2 3/4] USB: dwc3: Initial back port of dwc3 code

25 Jun 2013

+Felipe
He the right person to comment on this.
cheers,
-roger
On 06/24/2013 07:43 PM, Dan Murphy wrote:
...
This is the initial back port of the linux kernel
usb dwc3 code based on commit
commit 3b9561e9d9b88eca9d4ed6aab025dec2eeeed501
All code not applicable to uBoot is ifdef'd out with
ifndef __UBOOT__ as it is done in the musb-new directory.
This code has not been fully debuged or excersized.
Signed-off-by: Dan Murphy dmurphy@ti.com
Makefile                      |    1 +
 drivers/usb/dwc3/Makefile     |   53 +
 drivers/usb/dwc3/core.c       |  847 +++++++++++++
 drivers/usb/dwc3/core.h       |  974 ++++++++++++++
 drivers/usb/dwc3/dwc3-omap.c  |  505 ++++++++
 drivers/usb/dwc3/dwc3-omap.h  |   41 +
 drivers/usb/dwc3/dwc3-uboot.c |  384 ++++++
 drivers/usb/dwc3/ep0.c        | 1085 ++++++++++++++++
 drivers/usb/dwc3/gadget.c     | 2806 +++++++++++++++++++++++++++++++++++++++++
 drivers/usb/dwc3/gadget.h     |  196 +++
 drivers/usb/dwc3/host.c       |  107 ++
 drivers/usb/dwc3/io.h         |   81 ++
 12 files changed, 7080 insertions(+)
 create mode 100644 drivers/usb/dwc3/Makefile
 create mode 100644 drivers/usb/dwc3/core.c
 create mode 100644 drivers/usb/dwc3/core.h
 create mode 100644 drivers/usb/dwc3/dwc3-omap.c
 create mode 100644 drivers/usb/dwc3/dwc3-omap.h
 create mode 100644 drivers/usb/dwc3/dwc3-uboot.c
 create mode 100644 drivers/usb/dwc3/ep0.c
 create mode 100644 drivers/usb/dwc3/gadget.c
 create mode 100644 drivers/usb/dwc3/gadget.h
 create mode 100644 drivers/usb/dwc3/host.c
 create mode 100644 drivers/usb/dwc3/io.h

diff --git a/Makefile b/Makefile
index 693b3f2..29643f3 100644
--- a/Makefile
+++ b/Makefile
@@ -327,6 +327,7 @@ LIBS-y += drivers/usb/gadget/libusb_gadget.o
 LIBS-y += drivers/usb/host/libusb_host.o
 LIBS-y += drivers/usb/musb/libusb_musb.o
 LIBS-y += drivers/usb/musb-new/libusb_musb-new.o
+LIBS-y += drivers/usb/dwc3/libusb_dwc3.o
 LIBS-y += drivers/usb/phy/libusb_phy.o
 LIBS-y += drivers/usb/ulpi/libusb_ulpi.o
 LIBS-y += drivers/video/libvideo.o
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
new file mode 100644
index 0000000..0d589cc
--- /dev/null
+++ b/drivers/usb/dwc3/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2013
+# Texas Instruments Incorporated.
+#
+# Author: Dan Murphy dmurphy@ti.com
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#



+include $(TOPDIR)/config.mk



+LIB	:= $(obj)libusb_dwc3.o



+COBJS-$(CONFIG_USB_DWC3) += core.o dwc3-uboot.o
+COBJS-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
+COBJS-$(CONFIG_USB_DWC3_HOST) += host.o
+COBJS-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o



+CFLAGS_NO_WARN := $(call cc-option,-Wno-unused-variable) \

	$(call cc-option,-Wno-unused-label)



+CFLAGS += $(CFLAGS_NO_WARN)



+COBJS	:= $(COBJS-y)
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))



+all:	$(LIB)



+$(LIB):	$(obj).depend $(OBJS)

$(call cmd_link_o_target, $(OBJS))


+#########################################################################



+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk



+sinclude $(obj).depend



+#########################################################################



diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
new file mode 100644
index 0000000..8f042d4
--- /dev/null
+++ b/drivers/usb/dwc3/core.c
@@ -0,0 +1,847 @@
+/**


core.c - DesignWare USB3 DRD Controller Core file







Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com







Authors: Felipe Balbi balbi@ti.com,



   Sebastian Andrzej Siewior <bigeasy@linutronix.de>









Back-ported by: Dan Murphy dmurphy@ti.com







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions, and the following disclaimer,



without modification.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




The names of the above-listed copyright holders may not be used





to endorse or promote products derived from this software without



specific prior written permission.







ALTERNATIVELY, this software may be distributed under the terms of the



GNU General Public License ("GPL") version 2, as published by the Free



Software Foundation.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS



IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,



THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR



PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR



CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,



EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,



PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR



PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF



LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING



NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS



SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


*/


+#define __UBOOT__
+#ifndef __UBOOT__
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/of.h>



+#include <linux/usb/otg.h>



+#else
+#include <common.h>



+#include <linux/err.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/linux-compat.h>



+#endif



+#include "core.h"
+#include "gadget.h"
+#include "io.h"



+#ifndef __UBOOT__
+/* TODO: Need to move over the debug files */
+#include "debug.h"
+#endif
+static char *maximum_speed = "super";
+module_param(maximum_speed, charp, 0);
+MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");



+/* -------------------------------------------------------------------------- */



+void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
+{

u32 reg;

reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
reg |= DWC3_GCTL_PRTCAPDIR(mode);
dwc3_writel(dwc->regs, DWC3_GCTL, reg);

+}



+/**


dwc3_core_soft_reset - Issues core soft reset and PHY reset



@dwc: pointer to our context structure


*/

+static void dwc3_core_soft_reset(struct dwc3 *dwc)
+{

u32		reg;

/* Before Resetting PHY, put Core in Reset */
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg |= DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);

/* Assert USB3 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

/* Assert USB2 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

+#ifndef __UBOOT__

/* FIX THIS DM */
usb_phy_init(dwc->usb2_phy);
usb_phy_init(dwc->usb3_phy);

+#endif

mdelay(100);

/* Clear USB3 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

/* Clear USB2 PHY reset */
reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

mdelay(100);

/* After PHYs are stable we can take Core out of reset state */
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc->regs, DWC3_GCTL, reg);

+}



+/**


dwc3_free_one_event_buffer - Frees one event buffer



@dwc: Pointer to our controller context structure



@evt: Pointer to event buffer to be freed


*/

+static void dwc3_free_one_event_buffer(struct dwc3 *dwc,

struct dwc3_event_buffer *evt)



+{

dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);

+}



+/**


dwc3_alloc_one_event_buffer - Allocates one event buffer structure



@dwc: Pointer to our controller context structure



@length: size of the event buffer







Returns a pointer to the allocated event buffer structure on success



otherwise ERR_PTR(errno).


*/

+static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,

unsigned length)



+{

struct dwc3_event_buffer	*evt;


+#ifndef __UBOOT__

evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);

+#else

evt = kzalloc(sizeof(*evt), GFP_KERNEL);

+#endif

if (!evt)
return ERR_PTR(-ENOMEM);



evt->dwc	= dwc;
evt->length	= length;
evt->buf	= dma_alloc_coherent(dwc->dev, length,
	&evt->dma, GFP_KERNEL);


if (!evt->buf)
return ERR_PTR(-ENOMEM);



return evt;

+}



+/**


dwc3_free_event_buffers - frees all allocated event buffers



@dwc: Pointer to our controller context structure


*/

+#ifndef __UBOOT__
+static void dwc3_free_event_buffers(struct dwc3 *dwc)
+#else
+void dwc3_free_event_buffers(struct dwc3 *dwc)
+#endif
+{

struct dwc3_event_buffer	*evt;
int i;

for (i = 0; i < dwc->num_event_buffers; i++) {
evt = dwc->ev_buffs[i];


if (evt)


	dwc3_free_one_event_buffer(dwc, evt);


}

+}



+/**


dwc3_alloc_event_buffers - Allocates @num event buffers of size @length



@dwc: pointer to our controller context structure



@length: size of event buffer







Returns 0 on success otherwise negative errno. In the error case, dwc



may contain some buffers allocated but not all which were requested.


*/

+#ifndef __UBOOT__
+static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
+#else
+int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
+#endif
+{

int			num;
int			i;

num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
dwc->num_event_buffers = num;

+#ifndef __UBOOT__

dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
	GFP_KERNEL);



+#else

dwc->ev_buffs = kzalloc(sizeof(*dwc->ev_buffs) * num, GFP_KERNEL);

+#endif

if (!dwc->ev_buffs) {
dev_err(dwc->dev, "can't allocate event buffers array\n");


return -ENOMEM;


}

for (i = 0; i < num; i++) {
struct dwc3_event_buffer	*evt;



evt = dwc3_alloc_one_event_buffer(dwc, length);


if (IS_ERR(evt)) {


	dev_err(dwc->dev, "can't allocate event buffer\n");


	return PTR_ERR(evt);


}


dwc->ev_buffs[i] = evt;


}

return 0;

+}



+/**


dwc3_event_buffers_setup - setup our allocated event buffers



@dwc: pointer to our controller context structure







Returns 0 on success otherwise negative errno.


*/

+#ifndef __UBOOT__
+static int dwc3_event_buffers_setup(struct dwc3 *dwc)
+#else
+int dwc3_event_buffers_setup(struct dwc3 *dwc)
+#endif



+{

struct dwc3_event_buffer	*evt;
int				n;

for (n = 0; n < dwc->num_event_buffers; n++) {
evt = dwc->ev_buffs[n];


dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",


		evt->buf, (unsigned long long) evt->dma,


		evt->length);



evt->lpos = 0;



dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),


		lower_32_bits(evt->dma));


dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),


		upper_32_bits(evt->dma));


dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),


		evt->length & 0xffff);


dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);


}

return 0;

+}
+#ifndef __UBOOT__
+static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
+#else
+void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
+#endif
+{

struct dwc3_event_buffer	*evt;
int				n;

for (n = 0; n < dwc->num_event_buffers; n++) {
evt = dwc->ev_buffs[n];



evt->lpos = 0;



dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);


dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);


dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);


dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);


}

+}



+static void dwc3_core_num_eps(struct dwc3 *dwc)
+{

struct dwc3_hwparams	*parms = &dwc->hwparams;

dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;

dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
	dwc->num_in_eps, dwc->num_out_eps);



+}
+#ifndef __UBOOT__
+static void dwc3_cache_hwparams(struct dwc3 *dwc)
+#else
+void dwc3_cache_hwparams(struct dwc3 *dwc)
+#endif
+{

struct dwc3_hwparams	*parms = &dwc->hwparams;

parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);

+}



+/**


dwc3_core_init - Low-level initialization of DWC3 Core



@dwc: Pointer to our controller context structure







Returns 0 on success otherwise negative errno.


*/

+#ifndef __UBOOT__
+static int dwc3_core_init(struct dwc3 *dwc)
+#else
+int dwc3_core_init(struct dwc3 *dwc)
+#endif
+{

unsigned long		timeout;
u32			reg;
int			ret;

reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
/* This should read as U3 followed by revision number */
if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");


ret = -ENODEV;


goto err0;


}
dwc->revision = reg;

/* issue device SoftReset too */

+#ifndef __UBOOT__

timeout = jiffies + msecs_to_jiffies(500);

+#else

timeout = 500;

+#endif

dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
do {
reg = dwc3_readl(dwc->regs, DWC3_DCTL);


if (!(reg & DWC3_DCTL_CSFTRST))


	break;




+#ifndef __UBOOT__

if (time_after(jiffies, timeout)) {



+#else

mdelay(1);


timeout--;



if (!timeout) {



+#endif

	dev_err(dwc->dev, "Reset Timed Out\n");


	ret = -ETIMEDOUT;


	goto err0;


}



cpu_relax();


} while (true);

dwc3_core_soft_reset(dwc);

reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
reg &= ~DWC3_GCTL_DISSCRAMBLE;

switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
reg &= ~DWC3_GCTL_DSBLCLKGTNG;


break;


default:
dev_dbg(dwc->dev, "No power optimization available\n");


}

/*
* WORKAROUND: DWC3 revisions <1.90a have a bug


* where the device can fail to connect at SuperSpeed


* and falls back to high-speed mode which causes


* the device to enter a Connect/Disconnect loop


*/


if (dwc->revision < DWC3_REVISION_190A)
reg |= DWC3_GCTL_U2RSTECN;



dwc3_core_num_eps(dwc);

dwc3_writel(dwc->regs, DWC3_GCTL, reg);

return 0;


+err0:

return ret;

+}
+#ifndef __UBOOT__
+static void dwc3_core_exit(struct dwc3 *dwc)
+#else
+void dwc3_core_exit(struct dwc3 *dwc)
+#endif
+{
+#ifndef __UBOOT__

/* FIX THIS DM */
usb_phy_shutdown(dwc->usb2_phy);
usb_phy_shutdown(dwc->usb3_phy);

+#endif
+}



+#ifndef __UBOOT__
+#define DWC3_ALIGN_MASK		(16 - 1)



+static int dwc3_probe(struct platform_device *pdev)
+{

struct device_node	*node = pdev->dev.of_node;
struct resource		*res;
struct dwc3		*dwc;
struct device		*dev = &pdev->dev;

int			ret = -ENOMEM;

void __iomem		*regs;
void			*mem;

u8			mode;

mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
if (!mem) {
dev_err(dev, "not enough memory\n");


return -ENOMEM;


}
dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
dwc->mem = mem;

res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (!res) {
dev_err(dev, "missing IRQ\n");


return -ENODEV;


}
dwc->xhci_resources[1].start = res->start;
dwc->xhci_resources[1].end = res->end;
dwc->xhci_resources[1].flags = res->flags;
dwc->xhci_resources[1].name = res->name;

res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "missing memory resource\n");


return -ENODEV;


}
dwc->xhci_resources[0].start = res->start;
dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
			DWC3_XHCI_REGS_END;


dwc->xhci_resources[0].flags = res->flags;
dwc->xhci_resources[0].name = res->name;

/*


 * Request memory region but exclude xHCI regs,


 * since it will be requested by the xhci-plat driver.


 */


res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
	resource_size(res) - DWC3_GLOBALS_REGS_START,


	dev_name(dev));


if (!res) {
dev_err(dev, "can't request mem region\n");


return -ENOMEM;


}

regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
if (!regs) {
dev_err(dev, "ioremap failed\n");


return -ENOMEM;


}

if (node) {
dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);


dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);


} else {
dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);


dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);


}

if (IS_ERR(dwc->usb2_phy)) {
ret = PTR_ERR(dwc->usb2_phy);



/*


 * if -ENXIO is returned, it means PHY layer wasn't


 * enabled, so it makes no sense to return -EPROBE_DEFER


 * in that case, since no PHY driver will ever probe.


 */


if (ret == -ENXIO)


	return ret;



dev_err(dev, "no usb2 phy configured\n");


return -EPROBE_DEFER;


}

if (IS_ERR(dwc->usb3_phy)) {
ret = PTR_ERR(dwc->usb2_phy);



/*


 * if -ENXIO is returned, it means PHY layer wasn't


 * enabled, so it makes no sense to return -EPROBE_DEFER


 * in that case, since no PHY driver will ever probe.


 */


if (ret == -ENXIO)


	return ret;



dev_err(dev, "no usb3 phy configured\n");


return -EPROBE_DEFER;


}

usb_phy_set_suspend(dwc->usb2_phy, 0);
usb_phy_set_suspend(dwc->usb3_phy, 0);

spin_lock_init(&dwc->lock);
platform_set_drvdata(pdev, dwc);

dwc->regs	= regs;
dwc->regs_size	= resource_size(res);
dwc->dev	= dev;

dev->dma_mask	= dev->parent->dma_mask;
dev->dma_parms	= dev->parent->dma_parms;
dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);

if (!strncmp("super", maximum_speed, 5))
dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;


else if (!strncmp("high", maximum_speed, 4))
dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;


else if (!strncmp("full", maximum_speed, 4))
dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;


else if (!strncmp("low", maximum_speed, 3))
dwc->maximum_speed = DWC3_DCFG_LOWSPEED;


else
dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;



dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");

pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
pm_runtime_forbid(dev);

dwc3_cache_hwparams(dwc);

ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
if (ret) {
dev_err(dwc->dev, "failed to allocate event buffers\n");


ret = -ENOMEM;


goto err0;


}

ret = dwc3_core_init(dwc);
if (ret) {
dev_err(dev, "failed to initialize core\n");


goto err0;


}

ret = dwc3_event_buffers_setup(dwc);
if (ret) {
dev_err(dwc->dev, "failed to setup event buffers\n");


goto err1;


}

if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
mode = DWC3_MODE_HOST;


else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
mode = DWC3_MODE_DEVICE;


else
mode = DWC3_MODE_DRD;



switch (mode) {
case DWC3_MODE_DEVICE:
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);


ret = dwc3_gadget_init(dwc);


if (ret) {


	dev_err(dev, "failed to initialize gadget\n");


	goto err2;


}


break;


case DWC3_MODE_HOST:
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);


ret = dwc3_host_init(dwc);


if (ret) {


	dev_err(dev, "failed to initialize host\n");


	goto err2;


}


break;


case DWC3_MODE_DRD:
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);


ret = dwc3_host_init(dwc);


if (ret) {


	dev_err(dev, "failed to initialize host\n");


	goto err2;


}



ret = dwc3_gadget_init(dwc);


if (ret) {


	dev_err(dev, "failed to initialize gadget\n");


	goto err2;


}


break;


default:
dev_err(dev, "Unsupported mode of operation %d\n", mode);


goto err2;


}
dwc->mode = mode;

ret = dwc3_debugfs_init(dwc);
if (ret) {
dev_err(dev, "failed to initialize debugfs\n");


goto err3;


}

pm_runtime_allow(dev);

return 0;


+err3:

switch (mode) {
case DWC3_MODE_DEVICE:
dwc3_gadget_exit(dwc);


break;


case DWC3_MODE_HOST:
dwc3_host_exit(dwc);


break;


case DWC3_MODE_DRD:
dwc3_host_exit(dwc);


dwc3_gadget_exit(dwc);


break;


default:
/* do nothing */


break;


}


+err2:

dwc3_event_buffers_cleanup(dwc);


+err1:

dwc3_core_exit(dwc);


+err0:

dwc3_free_event_buffers(dwc);

return ret;

+}



+static int dwc3_remove(struct platform_device *pdev)
+{

struct dwc3	*dwc = platform_get_drvdata(pdev);

usb_phy_set_suspend(dwc->usb2_phy, 1);
usb_phy_set_suspend(dwc->usb3_phy, 1);

pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);

dwc3_debugfs_exit(dwc);

switch (dwc->mode) {
case DWC3_MODE_DEVICE:
dwc3_gadget_exit(dwc);


break;


case DWC3_MODE_HOST:
dwc3_host_exit(dwc);


break;


case DWC3_MODE_DRD:
dwc3_host_exit(dwc);


dwc3_gadget_exit(dwc);


break;


default:
/* do nothing */


break;


}

dwc3_event_buffers_cleanup(dwc);
dwc3_free_event_buffers(dwc);
dwc3_core_exit(dwc);

return 0;

+}



+#ifdef CONFIG_PM_SLEEP
+static int dwc3_prepare(struct device *dev)
+{

struct dwc3	*dwc = dev_get_drvdata(dev);
unsigned long	flags;

spin_lock_irqsave(&dwc->lock, flags);

switch (dwc->mode) {
case DWC3_MODE_DEVICE:
case DWC3_MODE_DRD:
dwc3_gadget_prepare(dwc);


/* FALLTHROUGH */


case DWC3_MODE_HOST:
default:
dwc3_event_buffers_cleanup(dwc);


break;


}

spin_unlock_irqrestore(&dwc->lock, flags);

return 0;

+}



+static void dwc3_complete(struct device *dev)
+{

struct dwc3	*dwc = dev_get_drvdata(dev);
unsigned long	flags;

spin_lock_irqsave(&dwc->lock, flags);

switch (dwc->mode) {
case DWC3_MODE_DEVICE:
case DWC3_MODE_DRD:
dwc3_gadget_complete(dwc);


/* FALLTHROUGH */


case DWC3_MODE_HOST:
default:
dwc3_event_buffers_setup(dwc);


break;


}

spin_unlock_irqrestore(&dwc->lock, flags);

+}



+static int dwc3_suspend(struct device *dev)
+{

struct dwc3	*dwc = dev_get_drvdata(dev);
unsigned long	flags;

spin_lock_irqsave(&dwc->lock, flags);

switch (dwc->mode) {
case DWC3_MODE_DEVICE:
case DWC3_MODE_DRD:
dwc3_gadget_suspend(dwc);


/* FALLTHROUGH */


case DWC3_MODE_HOST:
default:
/* do nothing */


break;


}

dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
spin_unlock_irqrestore(&dwc->lock, flags);

+#ifndef __UBOOT__

/* FIX THIS DM */
usb_phy_shutdown(dwc->usb3_phy);
usb_phy_shutdown(dwc->usb2_phy);

+#endif

return 0;

+}



+static int dwc3_resume(struct device *dev)
+{

struct dwc3	*dwc = dev_get_drvdata(dev);
unsigned long	flags;

+#ifndef __UBOOT__

/* FIX THIS DM */
usb_phy_init(dwc->usb3_phy);
usb_phy_init(dwc->usb2_phy);

+#endif

msleep(100);

spin_lock_irqsave(&dwc->lock, flags);

dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);

switch (dwc->mode) {
case DWC3_MODE_DEVICE:
case DWC3_MODE_DRD:
dwc3_gadget_resume(dwc);


/* FALLTHROUGH */


case DWC3_MODE_HOST:
default:
/* do nothing */


break;


}

spin_unlock_irqrestore(&dwc->lock, flags);

pm_runtime_disable(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);

return 0;

+}



+static const struct dev_pm_ops dwc3_dev_pm_ops = {

.prepare	= dwc3_prepare,
.complete	= dwc3_complete,

SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)

+};



+#define DWC3_PM_OPS	&(dwc3_dev_pm_ops)
+#else
+#define DWC3_PM_OPS	NULL
+#endif



+#ifdef CONFIG_OF
+static const struct of_device_id of_dwc3_match[] = {

{
.compatible = "synopsys,dwc3"


},
{ },

+};
+MODULE_DEVICE_TABLE(of, of_dwc3_match);
+#endif



+static struct platform_driver dwc3_driver = {

.probe		= dwc3_probe,
.remove		= dwc3_remove,
.driver		= {
.name	= "dwc3",


.of_match_table	= of_match_ptr(of_dwc3_match),


.pm	= DWC3_PM_OPS,


},

+};



+module_platform_driver(dwc3_driver);



+#endif /* __UBOOT__ */
+MODULE_ALIAS("platform:dwc3");
+MODULE_AUTHOR("Felipe Balbi balbi@ti.com");
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
new file mode 100644
index 0000000..154ffc5
--- /dev/null
+++ b/drivers/usb/dwc3/core.h
@@ -0,0 +1,974 @@
+/**


core.h - DesignWare USB3 DRD Core Header







Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com







Authors: Felipe Balbi balbi@ti.com,



   Sebastian Andrzej Siewior <bigeasy@linutronix.de>









Back-ported by: Dan Murphy dmurphy@ti.com







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions, and the following disclaimer,



without modification.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




The names of the above-listed copyright holders may not be used





to endorse or promote products derived from this software without



specific prior written permission.







ALTERNATIVELY, this software may be distributed under the terms of the



GNU General Public License ("GPL") version 2, as published by the Free



Software Foundation.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS



IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,



THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR



PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR



CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,



EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,



PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR



PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF



LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING



NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS



SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


*/


+#ifndef __DRIVERS_USB_DWC3_CORE_H
+#define __DRIVERS_USB_DWC3_CORE_H



+#define __UBOOT__
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/spinlock.h>
+#include <linux/ioport.h>
+#include <linux/list.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/debugfs.h>



+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#else



+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/compiler.h>
+#include <linux/usb/linux-compat.h>



+#endif



+/* Global constants */
+#define DWC3_EP0_BOUNCE_SIZE	512
+#define DWC3_ENDPOINTS_NUM	32
+#define DWC3_XHCI_RESOURCES_NUM	2



+#define DWC3_EVENT_SIZE		4	/* bytes */
+#define DWC3_EVENT_MAX_NUM	64	/* 2 events/endpoint */
+#define DWC3_EVENT_BUFFERS_SIZE	(DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
+#define DWC3_EVENT_TYPE_MASK	0xfe



+#define DWC3_EVENT_TYPE_DEV	0
+#define DWC3_EVENT_TYPE_CARKIT	3
+#define DWC3_EVENT_TYPE_I2C	4



+#define DWC3_DEVICE_EVENT_DISCONNECT		0
+#define DWC3_DEVICE_EVENT_RESET			1
+#define DWC3_DEVICE_EVENT_CONNECT_DONE		2
+#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
+#define DWC3_DEVICE_EVENT_WAKEUP		4
+#define DWC3_DEVICE_EVENT_HIBER_REQ		5
+#define DWC3_DEVICE_EVENT_EOPF			6
+#define DWC3_DEVICE_EVENT_SOF			7
+#define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
+#define DWC3_DEVICE_EVENT_CMD_CMPL		10
+#define DWC3_DEVICE_EVENT_OVERFLOW		11



+#define DWC3_GEVNTCOUNT_MASK	0xfffc
+#define DWC3_GSNPSID_MASK	0xffff0000
+#define DWC3_GSNPSREV_MASK	0xffff



+/* DWC3 registers memory space boundries */
+#define DWC3_XHCI_REGS_START		0x0
+#define DWC3_XHCI_REGS_END		0x7fff
+#define DWC3_GLOBALS_REGS_START		0xc100
+#define DWC3_GLOBALS_REGS_END		0xc6ff
+#define DWC3_DEVICE_REGS_START		0xc700
+#define DWC3_DEVICE_REGS_END		0xcbff
+#define DWC3_OTG_REGS_START		0xcc00
+#define DWC3_OTG_REGS_END		0xccff



+/* Global Registers */
+#define DWC3_GSBUSCFG0		0xc100
+#define DWC3_GSBUSCFG1		0xc104
+#define DWC3_GTXTHRCFG		0xc108
+#define DWC3_GRXTHRCFG		0xc10c
+#define DWC3_GCTL		0xc110
+#define DWC3_GEVTEN		0xc114
+#define DWC3_GSTS		0xc118
+#define DWC3_GSNPSID		0xc120
+#define DWC3_GGPIO		0xc124
+#define DWC3_GUID		0xc128
+#define DWC3_GUCTL		0xc12c
+#define DWC3_GBUSERRADDR0	0xc130
+#define DWC3_GBUSERRADDR1	0xc134
+#define DWC3_GPRTBIMAP0		0xc138
+#define DWC3_GPRTBIMAP1		0xc13c
+#define DWC3_GHWPARAMS0		0xc140
+#define DWC3_GHWPARAMS1		0xc144
+#define DWC3_GHWPARAMS2		0xc148
+#define DWC3_GHWPARAMS3		0xc14c
+#define DWC3_GHWPARAMS4		0xc150
+#define DWC3_GHWPARAMS5		0xc154
+#define DWC3_GHWPARAMS6		0xc158
+#define DWC3_GHWPARAMS7		0xc15c
+#define DWC3_GDBGFIFOSPACE	0xc160
+#define DWC3_GDBGLTSSM		0xc164
+#define DWC3_GPRTBIMAP_HS0	0xc180
+#define DWC3_GPRTBIMAP_HS1	0xc184
+#define DWC3_GPRTBIMAP_FS0	0xc188
+#define DWC3_GPRTBIMAP_FS1	0xc18c



+#define DWC3_GUSB2PHYCFG(n)	(0xc200 + (n * 0x04))
+#define DWC3_GUSB2I2CCTL(n)	(0xc240 + (n * 0x04))



+#define DWC3_GUSB2PHYACC(n)	(0xc280 + (n * 0x04))



+#define DWC3_GUSB3PIPECTL(n)	(0xc2c0 + (n * 0x04))



+#define DWC3_GTXFIFOSIZ(n)	(0xc300 + (n * 0x04))
+#define DWC3_GRXFIFOSIZ(n)	(0xc380 + (n * 0x04))



+#define DWC3_GEVNTADRLO(n)	(0xc400 + (n * 0x10))
+#define DWC3_GEVNTADRHI(n)	(0xc404 + (n * 0x10))
+#define DWC3_GEVNTSIZ(n)	(0xc408 + (n * 0x10))
+#define DWC3_GEVNTCOUNT(n)	(0xc40c + (n * 0x10))



+#define DWC3_GHWPARAMS8		0xc600



+/* Device Registers */
+#define DWC3_DCFG		0xc700
+#define DWC3_DCTL		0xc704
+#define DWC3_DEVTEN		0xc708
+#define DWC3_DSTS		0xc70c
+#define DWC3_DGCMDPAR		0xc710
+#define DWC3_DGCMD		0xc714
+#define DWC3_DALEPENA		0xc720
+#define DWC3_DEPCMDPAR2(n)	(0xc800 + (n * 0x10))
+#define DWC3_DEPCMDPAR1(n)	(0xc804 + (n * 0x10))
+#define DWC3_DEPCMDPAR0(n)	(0xc808 + (n * 0x10))
+#define DWC3_DEPCMD(n)		(0xc80c + (n * 0x10))



+/* OTG Registers */
+#define DWC3_OCFG		0xcc00
+#define DWC3_OCTL		0xcc04
+#define DWC3_OEVT		0xcc08
+#define DWC3_OEVTEN		0xcc0C
+#define DWC3_OSTS		0xcc10



+/* Bit fields */



+/* Global Configuration Register */
+#define DWC3_GCTL_PWRDNSCALE(n)	((n) << 19)
+#define DWC3_GCTL_U2RSTECN	(1 << 16)
+#define DWC3_GCTL_RAMCLKSEL(x)	(((x) & DWC3_GCTL_CLK_MASK) << 6)
+#define DWC3_GCTL_CLK_BUS	(0)
+#define DWC3_GCTL_CLK_PIPE	(1)
+#define DWC3_GCTL_CLK_PIPEHALF	(2)
+#define DWC3_GCTL_CLK_MASK	(3)



+#define DWC3_GCTL_PRTCAP(n)	(((n) & (3 << 12)) >> 12)
+#define DWC3_GCTL_PRTCAPDIR(n)	((n) << 12)
+#define DWC3_GCTL_PRTCAP_HOST	1
+#define DWC3_GCTL_PRTCAP_DEVICE	2
+#define DWC3_GCTL_PRTCAP_OTG	3



+#define DWC3_GCTL_CORESOFTRESET		(1 << 11)
+#define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
+#define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
+#define DWC3_GCTL_DISSCRAMBLE		(1 << 3)
+#define DWC3_GCTL_GBLHIBERNATIONEN	(1 << 1)
+#define DWC3_GCTL_DSBLCLKGTNG		(1 << 0)



+/* Global USB2 PHY Configuration Register */
+#define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
+#define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)



+/* Global USB3 PIPE Control Register */
+#define DWC3_GUSB3PIPECTL_PHYSOFTRST	(1 << 31)
+#define DWC3_GUSB3PIPECTL_SUSPHY	(1 << 17)



+/* Global TX Fifo Size Register */
+#define DWC3_GTXFIFOSIZ_TXFDEF(n)	((n) & 0xffff)
+#define DWC3_GTXFIFOSIZ_TXFSTADDR(n)	((n) & 0xffff0000)



+/* Global HWPARAMS1 Register */
+#define DWC3_GHWPARAMS1_EN_PWROPT(n)	(((n) & (3 << 24)) >> 24)
+#define DWC3_GHWPARAMS1_EN_PWROPT_NO	0
+#define DWC3_GHWPARAMS1_EN_PWROPT_CLK	1
+#define DWC3_GHWPARAMS1_EN_PWROPT_HIB	2
+#define DWC3_GHWPARAMS1_PWROPT(n)	((n) << 24)
+#define DWC3_GHWPARAMS1_PWROPT_MASK	DWC3_GHWPARAMS1_PWROPT(3)



+/* Global HWPARAMS4 Register */
+#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)	(((n) & (0x0f << 13)) >> 13)
+#define DWC3_MAX_HIBER_SCRATCHBUFS		15



+/* Device Configuration Register */
+#define DWC3_DCFG_LPM_CAP	(1 << 22)
+#define DWC3_DCFG_DEVADDR(addr)	((addr) << 3)
+#define DWC3_DCFG_DEVADDR_MASK	DWC3_DCFG_DEVADDR(0x7f)



+#define DWC3_DCFG_SPEED_MASK	(7 << 0)
+#define DWC3_DCFG_SUPERSPEED	(4 << 0)
+#define DWC3_DCFG_HIGHSPEED	(0 << 0)
+#define DWC3_DCFG_FULLSPEED2	(1 << 0)
+#define DWC3_DCFG_LOWSPEED	(2 << 0)
+#define DWC3_DCFG_FULLSPEED1	(3 << 0)



+#define DWC3_DCFG_LPM_CAP	(1 << 22)



+/* Device Control Register */
+#define DWC3_DCTL_RUN_STOP	(1 << 31)
+#define DWC3_DCTL_CSFTRST	(1 << 30)
+#define DWC3_DCTL_LSFTRST	(1 << 29)



+#define DWC3_DCTL_HIRD_THRES_MASK	(0x1f << 24)
+#define DWC3_DCTL_HIRD_THRES(n)	((n) << 24)



+#define DWC3_DCTL_APPL1RES	(1 << 23)



+/* These apply for core versions 1.87a and earlier */
+#define DWC3_DCTL_TRGTULST_MASK		(0x0f << 17)
+#define DWC3_DCTL_TRGTULST(n)		((n) << 17)
+#define DWC3_DCTL_TRGTULST_U2		(DWC3_DCTL_TRGTULST(2))
+#define DWC3_DCTL_TRGTULST_U3		(DWC3_DCTL_TRGTULST(3))
+#define DWC3_DCTL_TRGTULST_SS_DIS	(DWC3_DCTL_TRGTULST(4))
+#define DWC3_DCTL_TRGTULST_RX_DET	(DWC3_DCTL_TRGTULST(5))
+#define DWC3_DCTL_TRGTULST_SS_INACT	(DWC3_DCTL_TRGTULST(6))



+/* These apply for core versions 1.94a and later */
+#define DWC3_DCTL_KEEP_CONNECT	(1 << 19)
+#define DWC3_DCTL_L1_HIBER_EN	(1 << 18)
+#define DWC3_DCTL_CRS		(1 << 17)
+#define DWC3_DCTL_CSS		(1 << 16)



+#define DWC3_DCTL_INITU2ENA	(1 << 12)
+#define DWC3_DCTL_ACCEPTU2ENA	(1 << 11)
+#define DWC3_DCTL_INITU1ENA	(1 << 10)
+#define DWC3_DCTL_ACCEPTU1ENA	(1 << 9)
+#define DWC3_DCTL_TSTCTRL_MASK	(0xf << 1)



+#define DWC3_DCTL_ULSTCHNGREQ_MASK	(0x0f << 5)
+#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)



+#define DWC3_DCTL_ULSTCHNG_NO_ACTION	(DWC3_DCTL_ULSTCHNGREQ(0))
+#define DWC3_DCTL_ULSTCHNG_SS_DISABLED	(DWC3_DCTL_ULSTCHNGREQ(4))
+#define DWC3_DCTL_ULSTCHNG_RX_DETECT	(DWC3_DCTL_ULSTCHNGREQ(5))
+#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE	(DWC3_DCTL_ULSTCHNGREQ(6))
+#define DWC3_DCTL_ULSTCHNG_RECOVERY	(DWC3_DCTL_ULSTCHNGREQ(8))
+#define DWC3_DCTL_ULSTCHNG_COMPLIANCE	(DWC3_DCTL_ULSTCHNGREQ(10))
+#define DWC3_DCTL_ULSTCHNG_LOOPBACK	(DWC3_DCTL_ULSTCHNGREQ(11))



+/* Device Event Enable Register */
+#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN	(1 << 12)
+#define DWC3_DEVTEN_EVNTOVERFLOWEN	(1 << 11)
+#define DWC3_DEVTEN_CMDCMPLTEN		(1 << 10)
+#define DWC3_DEVTEN_ERRTICERREN		(1 << 9)
+#define DWC3_DEVTEN_SOFEN		(1 << 7)
+#define DWC3_DEVTEN_EOPFEN		(1 << 6)
+#define DWC3_DEVTEN_HIBERNATIONREQEVTEN	(1 << 5)
+#define DWC3_DEVTEN_WKUPEVTEN		(1 << 4)
+#define DWC3_DEVTEN_ULSTCNGEN		(1 << 3)
+#define DWC3_DEVTEN_CONNECTDONEEN	(1 << 2)
+#define DWC3_DEVTEN_USBRSTEN		(1 << 1)
+#define DWC3_DEVTEN_DISCONNEVTEN	(1 << 0)



+/* Device Status Register */
+#define DWC3_DSTS_DCNRD			(1 << 29)



+/* This applies for core versions 1.87a and earlier */
+#define DWC3_DSTS_PWRUPREQ		(1 << 24)



+/* These apply for core versions 1.94a and later */
+#define DWC3_DSTS_RSS			(1 << 25)
+#define DWC3_DSTS_SSS			(1 << 24)



+#define DWC3_DSTS_COREIDLE		(1 << 23)
+#define DWC3_DSTS_DEVCTRLHLT		(1 << 22)



+#define DWC3_DSTS_USBLNKST_MASK		(0x0f << 18)
+#define DWC3_DSTS_USBLNKST(n)		(((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)



+#define DWC3_DSTS_RXFIFOEMPTY		(1 << 17)



+#define DWC3_DSTS_SOFFN_MASK		(0x3fff << 3)
+#define DWC3_DSTS_SOFFN(n)		(((n) & DWC3_DSTS_SOFFN_MASK) >> 3)



+#define DWC3_DSTS_CONNECTSPD		(7 << 0)



+#define DWC3_DSTS_SUPERSPEED		(4 << 0)
+#define DWC3_DSTS_HIGHSPEED		(0 << 0)
+#define DWC3_DSTS_FULLSPEED2		(1 << 0)
+#define DWC3_DSTS_LOWSPEED		(2 << 0)
+#define DWC3_DSTS_FULLSPEED1		(3 << 0)



+/* Device Generic Command Register */
+#define DWC3_DGCMD_SET_LMP		0x01
+#define DWC3_DGCMD_SET_PERIODIC_PAR	0x02
+#define DWC3_DGCMD_XMIT_FUNCTION	0x03



+/* These apply for core versions 1.94a and later */
+#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO	0x04
+#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI	0x05



+#define DWC3_DGCMD_SELECTED_FIFO_FLUSH	0x09
+#define DWC3_DGCMD_ALL_FIFO_FLUSH	0x0a
+#define DWC3_DGCMD_SET_ENDPOINT_NRDY	0x0c
+#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK	0x10



+#define DWC3_DGCMD_STATUS(n)		(((n) >> 15) & 1)
+#define DWC3_DGCMD_CMDACT		(1 << 10)
+#define DWC3_DGCMD_CMDIOC		(1 << 8)



+/* Device Generic Command Parameter Register */
+#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT	(1 << 0)
+#define DWC3_DGCMDPAR_FIFO_NUM(n)		((n) << 0)
+#define DWC3_DGCMDPAR_RX_FIFO			(0 << 5)
+#define DWC3_DGCMDPAR_TX_FIFO			(1 << 5)
+#define DWC3_DGCMDPAR_LOOPBACK_DIS		(0 << 0)
+#define DWC3_DGCMDPAR_LOOPBACK_ENA		(1 << 0)



+/* Device Endpoint Command Register */
+#define DWC3_DEPCMD_PARAM_SHIFT		16
+#define DWC3_DEPCMD_PARAM(x)		((x) << DWC3_DEPCMD_PARAM_SHIFT)
+#define DWC3_DEPCMD_GET_RSC_IDX(x)     (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
+#define DWC3_DEPCMD_STATUS(x)		(((x) >> 15) & 1)
+#define DWC3_DEPCMD_HIPRI_FORCERM	(1 << 11)
+#define DWC3_DEPCMD_CMDACT		(1 << 10)
+#define DWC3_DEPCMD_CMDIOC		(1 << 8)



+#define DWC3_DEPCMD_DEPSTARTCFG		(0x09 << 0)
+#define DWC3_DEPCMD_ENDTRANSFER		(0x08 << 0)
+#define DWC3_DEPCMD_UPDATETRANSFER	(0x07 << 0)
+#define DWC3_DEPCMD_STARTTRANSFER	(0x06 << 0)
+#define DWC3_DEPCMD_CLEARSTALL		(0x05 << 0)
+#define DWC3_DEPCMD_SETSTALL		(0x04 << 0)
+/* This applies for core versions 1.90a and earlier */
+#define DWC3_DEPCMD_GETSEQNUMBER	(0x03 << 0)
+/* This applies for core versions 1.94a and later */
+#define DWC3_DEPCMD_GETEPSTATE		(0x03 << 0)
+#define DWC3_DEPCMD_SETTRANSFRESOURCE	(0x02 << 0)
+#define DWC3_DEPCMD_SETEPCONFIG		(0x01 << 0)



+/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
+#define DWC3_DALEPENA_EP(n)		(1 << n)



+#define DWC3_DEPCMD_TYPE_CONTROL	0
+#define DWC3_DEPCMD_TYPE_ISOC		1
+#define DWC3_DEPCMD_TYPE_BULK		2
+#define DWC3_DEPCMD_TYPE_INTR		3



+/* Structures */



+struct dwc3_trb;



+/**


struct dwc3_event_buffer - Software event buffer representation



@list: a list of event buffers



@buf: _THE_ buffer



@length: size of this buffer



@lpos: event offset



@count: cache of last read event count register



@flags: flags related to this event buffer



@dma: dma_addr_t



@dwc: pointer to DWC controller


*/

+struct dwc3_event_buffer {

void			*buf;
unsigned		length;
unsigned int		lpos;
unsigned int		count;
unsigned int		flags;


+#define DWC3_EVENT_PENDING	BIT(0)


dma_addr_t		dma;

struct dwc3		*dwc;

+};



+#define DWC3_EP_FLAG_STALLED	(1 << 0)
+#define DWC3_EP_FLAG_WEDGED	(1 << 1)



+#define DWC3_EP_DIRECTION_TX	true
+#define DWC3_EP_DIRECTION_RX	false



+#define DWC3_TRB_NUM		32
+#define DWC3_TRB_MASK		(DWC3_TRB_NUM - 1)



+/**


struct dwc3_ep - device side endpoint representation



@endpoint: usb endpoint



@request_list: list of requests for this endpoint



@req_queued: list of requests on this ep which have TRBs setup



@trb_pool: array of transaction buffers



@trb_pool_dma: dma address of @trb_pool



@free_slot: next slot which is going to be used



@busy_slot: first slot which is owned by HW



@desc: usb_endpoint_descriptor pointer



@dwc: pointer to DWC controller



@flags: endpoint flags (wedged, stalled, ...)



@current_trb: index of current used trb



@number: endpoint number (1 - 15)



@type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK



@resource_index: Resource transfer index



@interval: the intervall on which the ISOC transfer is started



@name: a human readable name e.g. ep1out-bulk



@direction: true for TX, false for RX



@stream_capable: true when streams are enabled


*/

+struct dwc3_ep {

struct usb_ep		endpoint;
struct list_head	request_list;
struct list_head	req_queued;

struct dwc3_trb		*trb_pool;
dma_addr_t		trb_pool_dma;
u32			free_slot;
u32			busy_slot;
const struct usb_ss_ep_comp_descriptor *comp_desc;
struct dwc3		*dwc;

unsigned		flags;

+#define DWC3_EP_ENABLED		(1 << 0)
+#define DWC3_EP_STALL		(1 << 1)
+#define DWC3_EP_WEDGE		(1 << 2)
+#define DWC3_EP_BUSY		(1 << 4)
+#define DWC3_EP_PENDING_REQUEST	(1 << 5)
+#define DWC3_EP_MISSED_ISOC	(1 << 6)


/* This last one is specific to EP0 */

+#define DWC3_EP0_DIR_IN		(1 << 31)


unsigned		current_trb;

u8			number;
u8			type;
u8			resource_index;
u32			interval;

char			name[20];

unsigned		direction:1;
unsigned		stream_capable:1;

+};



+enum dwc3_phy {

DWC3_PHY_UNKNOWN = 0,
DWC3_PHY_USB3,
DWC3_PHY_USB2,

+};



+enum dwc3_ep0_next {

DWC3_EP0_UNKNOWN = 0,
DWC3_EP0_COMPLETE,
DWC3_EP0_NRDY_DATA,
DWC3_EP0_NRDY_STATUS,

+};



+enum dwc3_ep0_state {

EP0_UNCONNECTED		= 0,
EP0_SETUP_PHASE,
EP0_DATA_PHASE,
EP0_STATUS_PHASE,

+};



+enum dwc3_link_state {

/* In SuperSpeed */
DWC3_LINK_STATE_U0		= 0x00, /* in HS, means ON */
DWC3_LINK_STATE_U1		= 0x01,
DWC3_LINK_STATE_U2		= 0x02, /* in HS, means SLEEP */
DWC3_LINK_STATE_U3		= 0x03, /* in HS, means SUSPEND */
DWC3_LINK_STATE_SS_DIS		= 0x04,
DWC3_LINK_STATE_RX_DET		= 0x05, /* in HS, means Early Suspend */
DWC3_LINK_STATE_SS_INACT	= 0x06,
DWC3_LINK_STATE_POLL		= 0x07,
DWC3_LINK_STATE_RECOV		= 0x08,
DWC3_LINK_STATE_HRESET		= 0x09,
DWC3_LINK_STATE_CMPLY		= 0x0a,
DWC3_LINK_STATE_LPBK		= 0x0b,
DWC3_LINK_STATE_RESET		= 0x0e,
DWC3_LINK_STATE_RESUME		= 0x0f,
DWC3_LINK_STATE_MASK		= 0x0f,

+};



+/* TRB Length, PCM and Status */
+#define DWC3_TRB_SIZE_MASK	(0x00ffffff)
+#define DWC3_TRB_SIZE_LENGTH(n)	((n) & DWC3_TRB_SIZE_MASK)
+#define DWC3_TRB_SIZE_PCM1(n)	(((n) & 0x03) << 24)
+#define DWC3_TRB_SIZE_TRBSTS(n)	(((n) & (0x0f << 28)) >> 28)



+#define DWC3_TRBSTS_OK			0
+#define DWC3_TRBSTS_MISSED_ISOC		1
+#define DWC3_TRBSTS_SETUP_PENDING	2
+#define DWC3_TRB_STS_XFER_IN_PROG	4



+/* TRB Control */
+#define DWC3_TRB_CTRL_HWO		(1 << 0)
+#define DWC3_TRB_CTRL_LST		(1 << 1)
+#define DWC3_TRB_CTRL_CHN		(1 << 2)
+#define DWC3_TRB_CTRL_CSP		(1 << 3)
+#define DWC3_TRB_CTRL_TRBCTL(n)		(((n) & 0x3f) << 4)
+#define DWC3_TRB_CTRL_ISP_IMI		(1 << 10)
+#define DWC3_TRB_CTRL_IOC		(1 << 11)
+#define DWC3_TRB_CTRL_SID_SOFN(n)	(((n) & 0xffff) << 14)



+#define DWC3_TRBCTL_NORMAL		DWC3_TRB_CTRL_TRBCTL(1)
+#define DWC3_TRBCTL_CONTROL_SETUP	DWC3_TRB_CTRL_TRBCTL(2)
+#define DWC3_TRBCTL_CONTROL_STATUS2	DWC3_TRB_CTRL_TRBCTL(3)
+#define DWC3_TRBCTL_CONTROL_STATUS3	DWC3_TRB_CTRL_TRBCTL(4)
+#define DWC3_TRBCTL_CONTROL_DATA	DWC3_TRB_CTRL_TRBCTL(5)
+#define DWC3_TRBCTL_ISOCHRONOUS_FIRST	DWC3_TRB_CTRL_TRBCTL(6)
+#define DWC3_TRBCTL_ISOCHRONOUS		DWC3_TRB_CTRL_TRBCTL(7)
+#define DWC3_TRBCTL_LINK_TRB		DWC3_TRB_CTRL_TRBCTL(8)



+/**


struct dwc3_trb - transfer request block (hw format)



@bpl: DW0-3



@bph: DW4-7



@size: DW8-B



@trl: DWC-F


*/

+struct dwc3_trb {

u32		bpl;
u32		bph;
u32		size;
u32		ctrl;

+} __packed;



+/**


dwc3_hwparams - copy of HWPARAMS registers



@hwparams0 - GHWPARAMS0



@hwparams1 - GHWPARAMS1



@hwparams2 - GHWPARAMS2



@hwparams3 - GHWPARAMS3



@hwparams4 - GHWPARAMS4



@hwparams5 - GHWPARAMS5



@hwparams6 - GHWPARAMS6



@hwparams7 - GHWPARAMS7



@hwparams8 - GHWPARAMS8


*/

+struct dwc3_hwparams {

u32	hwparams0;
u32	hwparams1;
u32	hwparams2;
u32	hwparams3;
u32	hwparams4;
u32	hwparams5;
u32	hwparams6;
u32	hwparams7;
u32	hwparams8;

+};



+/* HWPARAMS0 */
+#define DWC3_MODE(n)		((n) & 0x7)



+#define DWC3_MODE_DEVICE	0
+#define DWC3_MODE_HOST		1
+#define DWC3_MODE_DRD		2
+#define DWC3_MODE_HUB		3



+#define DWC3_MDWIDTH(n)		(((n) & 0xff00) >> 8)



+/* HWPARAMS1 */
+#define DWC3_NUM_INT(n)		(((n) & (0x3f << 15)) >> 15)



+/* HWPARAMS3 */
+#define DWC3_NUM_IN_EPS_MASK	(0x1f << 18)
+#define DWC3_NUM_EPS_MASK	(0x3f << 12)
+#define DWC3_NUM_EPS(p)		(((p)->hwparams3 &		\

	(DWC3_NUM_EPS_MASK)) >> 12)



+#define DWC3_NUM_IN_EPS(p)	(((p)->hwparams3 &		\

	(DWC3_NUM_IN_EPS_MASK)) >> 18)




+/* HWPARAMS7 */
+#define DWC3_RAM1_DEPTH(n)	((n) & 0xffff)



+struct dwc3_request {

struct usb_request	request;
struct list_head	list;
struct dwc3_ep		*dep;
u32			start_slot;

u8			epnum;
struct dwc3_trb		*trb;
dma_addr_t		trb_dma;

unsigned		direction:1;
unsigned		mapped:1;
unsigned		queued:1;

+};



+/*


struct dwc3_scratchpad_array - hibernation scratchpad array



(format defined by hw)


*/

+struct dwc3_scratchpad_array {

__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];

+};



+/**


struct dwc3 - representation of our controller



@ctrl_req: usb control request which is used for ep0



@ep0_trb: trb which is used for the ctrl_req



@ep0_bounce: bounce buffer for ep0



@setup_buf: used while precessing STD USB requests



@ctrl_req_addr: dma address of ctrl_req



@ep0_trb: dma address of ep0_trb



@ep0_usb_req: dummy req used while handling STD USB requests



@ep0_bounce_addr: dma address of ep0_bounce



@lock: for synchronizing



@dev: pointer to our struct device



@xhci: pointer to our xHCI child



@event_buffer_list: a list of event buffers



@gadget: device side representation of the peripheral controller



@gadget_driver: pointer to the gadget driver



@regs: base address for our registers



@regs_size: address space size



@num_event_buffers: calculated number of event buffers



@u1u2: only used on revisions <1.83a for workaround



@maximum_speed: maximum speed requested (mainly for testing purposes)



@revision: revision register contents



@mode: mode of operation



@usb2_phy: pointer to USB2 PHY



@usb3_phy: pointer to USB3 PHY



@dcfg: saved contents of DCFG register



@gctl: saved contents of GCTL register



@is_selfpowered: true when we are selfpowered



@three_stage_setup: set if we perform a three phase setup



@ep0_bounced: true when we used bounce buffer



@ep0_expect_in: true when we expect a DATA IN transfer



@start_config_issued: true when StartConfig command has been issued



@setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround



@needs_fifo_resize: not all users might want fifo resizing, flag it



@resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.



@isoch_delay: wValue from Set Isochronous Delay request;



@u2sel: parameter from Set SEL request.



@u2pel: parameter from Set SEL request.



@u1sel: parameter from Set SEL request.



@u1pel: parameter from Set SEL request.



@num_out_eps: number of out endpoints



@num_in_eps: number of in endpoints



@ep0_next_event: hold the next expected event



@ep0state: state of endpoint zero



@link_state: link state



@speed: device speed (super, high, full, low)



@mem: points to start of memory which is used for this struct.



@hwparams: copy of hwparams registers



@root: debugfs root folder pointer


*/

+struct dwc3 {

struct usb_ctrlrequest	*ctrl_req;
struct dwc3_trb		*ep0_trb;
void			*ep0_bounce;
u8			*setup_buf;
dma_addr_t		ctrl_req_addr;
dma_addr_t		ep0_trb_addr;
dma_addr_t		ep0_bounce_addr;
struct dwc3_request	ep0_usb_req;

/* device lock */
spinlock_t		lock;

struct device		*dev;

struct platform_device	*xhci;

+/*	struct resource		xhci_resources[DWC3_XHCI_RESOURCES_NUM]; */


struct dwc3_event_buffer **ev_buffs;
struct dwc3_ep		*eps[DWC3_ENDPOINTS_NUM];

struct usb_gadget	gadget;
struct usb_gadget_driver *gadget_driver;

struct usb_phy		*usb2_phy;
struct usb_phy		*usb3_phy;

void __iomem		*regs;
size_t			regs_size;

/* used for suspend/resume */
u32			dcfg;
u32			gctl;

u32			num_event_buffers;
u32			u1u2;
u32			maximum_speed;
u32			revision;
u32			mode;


+#define DWC3_REVISION_173A	0x5533173a
+#define DWC3_REVISION_175A	0x5533175a
+#define DWC3_REVISION_180A	0x5533180a
+#define DWC3_REVISION_183A	0x5533183a
+#define DWC3_REVISION_185A	0x5533185a
+#define DWC3_REVISION_187A	0x5533187a
+#define DWC3_REVISION_188A	0x5533188a
+#define DWC3_REVISION_190A	0x5533190a
+#define DWC3_REVISION_194A	0x5533194a
+#define DWC3_REVISION_200A	0x5533200a
+#define DWC3_REVISION_202A	0x5533202a
+#define DWC3_REVISION_210A	0x5533210a
+#define DWC3_REVISION_220A	0x5533220a
+#define DWC3_REVISION_230A	0x5533230a
+#define DWC3_REVISION_240A	0x5533240a
+#define DWC3_REVISION_250A	0x5533250a


unsigned		is_selfpowered:1;
unsigned		three_stage_setup:1;
unsigned		ep0_bounced:1;
unsigned		ep0_expect_in:1;
unsigned		start_config_issued:1;
unsigned		setup_packet_pending:1;
unsigned		delayed_status:1;
unsigned		needs_fifo_resize:1;
unsigned		resize_fifos:1;
unsigned		pullups_connected:1;

enum dwc3_ep0_next	ep0_next_event;
enum dwc3_ep0_state	ep0state;
enum dwc3_link_state	link_state;

u16			isoch_delay;
u16			u2sel;
u16			u2pel;
u8			u1sel;
u8			u1pel;

u8			speed;

u8			num_out_eps;
u8			num_in_eps;

void			*mem;

struct dwc3_hwparams	hwparams;
struct dentry		*root;
struct debugfs_regset32	*regset;

u8			test_mode;
u8			test_mode_nr;

+};



+/* -------------------------------------------------------------------------- */



+/* -------------------------------------------------------------------------- */



+struct dwc3_event_type {

u32	is_devspec:1;
u32	type:6;
u32	reserved8_31:25;

+} __packed;



+#define DWC3_DEPEVT_XFERCOMPLETE	0x01
+#define DWC3_DEPEVT_XFERINPROGRESS	0x02
+#define DWC3_DEPEVT_XFERNOTREADY	0x03
+#define DWC3_DEPEVT_RXTXFIFOEVT		0x04
+#define DWC3_DEPEVT_STREAMEVT		0x06
+#define DWC3_DEPEVT_EPCMDCMPLT		0x07



+/**


struct dwc3_event_depvt - Device Endpoint Events



@one_bit: indicates this is an endpoint event (not used)



@endpoint_number: number of the endpoint



@endpoint_event: The event we have:



0x00	- Reserved



0x01	- XferComplete



0x02	- XferInProgress



0x03	- XferNotReady



0x04	- RxTxFifoEvt (IN->Underrun, OUT->Overrun)



0x05	- Reserved



0x06	- StreamEvt



0x07	- EPCmdCmplt



@reserved11_10: Reserved, don't use.



@status: Indicates the status of the event. Refer to databook for



more information.



@parameters: Parameters of the current event. Refer to databook for



more information.


*/

+struct dwc3_event_depevt {

u32	one_bit:1;
u32	endpoint_number:5;
u32	endpoint_event:4;
u32	reserved11_10:2;
u32	status:4;


+/* Within XferNotReady */
+#define DEPEVT_STATUS_TRANSFER_ACTIVE	(1 << 3)



+/* Within XferComplete */
+#define DEPEVT_STATUS_BUSERR	(1 << 0)
+#define DEPEVT_STATUS_SHORT	(1 << 1)
+#define DEPEVT_STATUS_IOC	(1 << 2)
+#define DEPEVT_STATUS_LST	(1 << 3)



+/* Stream event only */
+#define DEPEVT_STREAMEVT_FOUND		1
+#define DEPEVT_STREAMEVT_NOTFOUND	2



+/* Control-only Status */
+#define DEPEVT_STATUS_CONTROL_DATA	1
+#define DEPEVT_STATUS_CONTROL_STATUS	2


u32	parameters:16;

+} __packed;



+/**


struct dwc3_event_devt - Device Events



@one_bit: indicates this is a non-endpoint event (not used)



@device_event: indicates it's a device event. Should read as 0x00



@type: indicates the type of device event.



0	- DisconnEvt



1	- USBRst



2	- ConnectDone



3	- ULStChng



4	- WkUpEvt



5	- Reserved



6	- EOPF



7	- SOF



8	- Reserved



9	- ErrticErr



10	- CmdCmplt



11	- EvntOverflow



12	- VndrDevTstRcved



@reserved15_12: Reserved, not used



@event_info: Information about this event



@reserved31_24: Reserved, not used


*/

+struct dwc3_event_devt {

u32	one_bit:1;
u32	device_event:7;
u32	type:4;
u32	reserved15_12:4;
u32	event_info:8;
u32	reserved31_24:8;

+} __packed;



+/**


struct dwc3_event_gevt - Other Core Events



@one_bit: indicates this is a non-endpoint event (not used)



@device_event: indicates it's (0x03) Carkit or (0x04) I2C event.



@phy_port_number: self-explanatory



@reserved31_12: Reserved, not used.


*/

+struct dwc3_event_gevt {

u32	one_bit:1;
u32	device_event:7;
u32	phy_port_number:4;
u32	reserved31_12:20;

+} __packed;



+/**


union dwc3_event - representation of Event Buffer contents



@raw: raw 32-bit event



@type: the type of the event



@depevt: Device Endpoint Event



@devt: Device Event



@gevt: Global Event


*/

+union dwc3_event {

u32				raw;
struct dwc3_event_type		type;
struct dwc3_event_depevt	depevt;
struct dwc3_event_devt		devt;
struct dwc3_event_gevt		gevt;

+};



+/*


DWC3 Features to be used as Driver Data


*/


+#define DWC3_HAS_PERIPHERAL		BIT(0)
+#define DWC3_HAS_XHCI			BIT(1)
+#define DWC3_HAS_OTG			BIT(3)



+/* prototypes */
+void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
+int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);



+/* TODO rework this for uboot 
+#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
+*/
+#if defined(CONFIG_USB_DWC3_HOST) || \

defined(CONFIG_USB_DWC3_DUAL_ROLE)

+int dwc3_host_init(struct dwc3 *dwc);
+void dwc3_host_exit(struct dwc3 *dwc);
+#else
+static inline int dwc3_host_init(struct dwc3 *dwc)
+{ return 0; }
+static inline void dwc3_host_exit(struct dwc3 *dwc)
+{ }
+#endif



+/* TODO rework this for uboot 
+#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
+*/
+#if defined(CONFIG_USB_DWC3_GADGET) || \

defined(CONFIG_USB_DWC3_DUAL_ROLE)

+int dwc3_gadget_init(struct dwc3 *dwc);
+void dwc3_gadget_exit(struct dwc3 *dwc);
+#else
+static inline int dwc3_gadget_init(struct dwc3 *dwc)
+{ return 0; }
+static inline void dwc3_gadget_exit(struct dwc3 *dwc)
+{ }
+#endif



+/* power management interface */
+/* TODO rework this for uboot 
+#if !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
+#if defined (CONFIG_USB_DWC3_HOST)
+int dwc3_gadget_prepare(struct dwc3 *dwc);
+void dwc3_gadget_complete(struct dwc3 *dwc);
+int dwc3_gadget_suspend(struct dwc3 *dwc);
+int dwc3_gadget_resume(struct dwc3 *dwc);
+#endif
+/*
+#else
+static inline int dwc3_gadget_prepare(struct dwc3 *dwc)
+{

return 0;

+}



+static inline void dwc3_gadget_complete(struct dwc3 *dwc)
+{
+}



+static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
+{

return 0;

+}



+static inline int dwc3_gadget_resume(struct dwc3 *dwc)
+{

return 0;

+}
+#endif 
+*/



+#ifdef __UBOOT__
+int dwc3_core_init(struct dwc3 *dwc);
+int dwc3_event_buffers_setup(struct dwc3 *dwc);
+void dwc3_core_exit(struct dwc3 *dwc);
+int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length);
+void dwc3_free_event_buffers(struct dwc3 *dwc);
+void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
+void dwc3_cache_hwparams(struct dwc3 *dwc);
+#endif



+#endif /* __DRIVERS_USB_DWC3_CORE_H */
diff --git a/drivers/usb/dwc3/dwc3-omap.c b/drivers/usb/dwc3/dwc3-omap.c
new file mode 100644
index 0000000..8432e18
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-omap.c
@@ -0,0 +1,505 @@
+/**


dwc3-omap.c - OMAP Specific Glue layer







Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com







Authors: Felipe Balbi balbi@ti.com,



   Sebastian Andrzej Siewior <bigeasy@linutronix.de>









Back-ported by: Dan Murphy dmurphy@ti.com







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions, and the following disclaimer,



without modification.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




The names of the above-listed copyright holders may not be used





to endorse or promote products derived from this software without



specific prior written permission.







ALTERNATIVELY, this software may be distributed under the terms of the



GNU General Public License ("GPL") version 2, as published by the Free



Software Foundation.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS



IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,



THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR



PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR



CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,



EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,



PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR



PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF



LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING



NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS



SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


*/


+#define __UBOOT__
+#ifndef __UBOOT__
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/dwc3-omap.h>
+#include <linux/usb/dwc3-omap.h>
+#include <linux/pm_runtime.h>
+#include <linux/dma-mapping.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/usb/otg.h>



+#else



+#include <linux/usb/linux-compat.h>
+#include <usb/lin_gadget_compat.h>



+#include "io.h"
+#include "dwc3-omap.h"



+#endif



+/*


All these registers belong to OMAP's Wrapper around the



DesignWare USB3 Core.


*/


+#define USBOTGSS_REVISION			0x0000
+#define USBOTGSS_SYSCONFIG			0x0010
+#define USBOTGSS_IRQ_EOI			0x0020
+#define USBOTGSS_IRQSTATUS_RAW_0		0x0024
+#define USBOTGSS_IRQSTATUS_0			0x0028
+#define USBOTGSS_IRQENABLE_SET_0		0x002c
+#define USBOTGSS_IRQENABLE_CLR_0		0x0030
+#define USBOTGSS_IRQSTATUS_RAW_1		0x0034
+#define USBOTGSS_IRQSTATUS_1			0x0038
+#define USBOTGSS_IRQENABLE_SET_1		0x003c
+#define USBOTGSS_IRQENABLE_CLR_1		0x0040
+#define USBOTGSS_UTMI_OTG_CTRL			0x0080
+#define USBOTGSS_UTMI_OTG_STATUS		0x0084
+#define USBOTGSS_MMRAM_OFFSET			0x0100
+#define USBOTGSS_FLADJ				0x0104
+#define USBOTGSS_DEBUG_CFG			0x0108
+#define USBOTGSS_DEBUG_DATA			0x010c



+/* SYSCONFIG REGISTER */
+#define USBOTGSS_SYSCONFIG_DMADISABLE		(1 << 16)



+/* IRQ_EOI REGISTER */
+#define USBOTGSS_IRQ_EOI_LINE_NUMBER		(1 << 0)



+/* IRQS0 BITS */
+#define USBOTGSS_IRQO_COREIRQ_ST		(1 << 0)



+/* IRQ1 BITS */
+#define USBOTGSS_IRQ1_DMADISABLECLR		(1 << 17)
+#define USBOTGSS_IRQ1_OEVT			(1 << 16)
+#define USBOTGSS_IRQ1_DRVVBUS_RISE		(1 << 13)
+#define USBOTGSS_IRQ1_CHRGVBUS_RISE		(1 << 12)
+#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE		(1 << 11)
+#define USBOTGSS_IRQ1_IDPULLUP_RISE		(1 << 8)
+#define USBOTGSS_IRQ1_DRVVBUS_FALL		(1 << 5)
+#define USBOTGSS_IRQ1_CHRGVBUS_FALL		(1 << 4)
+#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL		(1 << 3)
+#define USBOTGSS_IRQ1_IDPULLUP_FALL		(1 << 0)



+/* UTMI_OTG_CTRL REGISTER */
+#define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS		(1 << 5)
+#define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS		(1 << 4)
+#define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS	(1 << 3)
+#define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP		(1 << 0)



+/* UTMI_OTG_STATUS REGISTER */
+#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE	(1 << 31)
+#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT	(1 << 9)
+#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
+#define USBOTGSS_UTMI_OTG_STATUS_IDDIG		(1 << 4)
+#define USBOTGSS_UTMI_OTG_STATUS_SESSEND	(1 << 3)
+#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID	(1 << 2)
+#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID	(1 << 1)



+struct dwc3_omap {

/* device lock */
spinlock_t		lock;

struct device		*dev;

int			irq;
void __iomem		*base;

u32			utmi_otg_status;

u32			dma_status:1;

+};



+static struct dwc3_omap		*_omap;



+static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
+{

return readl(base + offset);

+}



+static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
+{

writel(value, base + offset);

+}



+int dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
+{

u32			val;
struct dwc3_omap	*omap = _omap;

if (!omap)

+#ifndef __UBOOT__

return -EPROBE_DEFER;



+#else

return -EINVAL;



+#endif


switch (status) {
case OMAP_DWC3_ID_GROUND:
dev_dbg(omap->dev, "ID GND\n");



val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);


val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG


		| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID


		| USBOTGSS_UTMI_OTG_STATUS_SESSEND);


val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID


		| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;


dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);


break;



case OMAP_DWC3_VBUS_VALID:
dev_dbg(omap->dev, "VBUS Connect\n");



val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);


val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;


val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG


		| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID


		| USBOTGSS_UTMI_OTG_STATUS_SESSVALID


		| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;


dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);


break;



case OMAP_DWC3_ID_FLOAT:
case OMAP_DWC3_VBUS_OFF:
dev_dbg(omap->dev, "VBUS Disconnect\n");



val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);


val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID


		| USBOTGSS_UTMI_OTG_STATUS_VBUSVALID


		| USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);


val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND


		| USBOTGSS_UTMI_OTG_STATUS_IDDIG;


dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);


break;



default:
dev_dbg(omap->dev, "ID float\n");


}

return 0;

+}
+EXPORT_SYMBOL_GPL(dwc3_omap_mailbox);



+static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
+{

struct dwc3_omap	*omap = _omap;
u32			reg;

spin_lock(&omap->lock);

reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);

if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
dev_dbg(omap->dev, "DMA Disable was Cleared\n");


omap->dma_status = false;


}

if (reg & USBOTGSS_IRQ1_OEVT)
dev_dbg(omap->dev, "OTG Event\n");



if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
dev_dbg(omap->dev, "DRVVBUS Rise\n");



if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
dev_dbg(omap->dev, "CHRGVBUS Rise\n");



if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");



if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
dev_dbg(omap->dev, "IDPULLUP Rise\n");



if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
dev_dbg(omap->dev, "DRVVBUS Fall\n");



if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
dev_dbg(omap->dev, "CHRGVBUS Fall\n");



if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");



if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
dev_dbg(omap->dev, "IDPULLUP Fall\n");



dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);

reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);

spin_unlock(&omap->lock);

return IRQ_HANDLED;

+}



+#ifndef __UBOOT__
+static int dwc3_omap_remove_core(struct device *dev, void *c)
+{

struct platform_device *pdev = to_platform_device(dev);

platform_device_unregister(pdev);

return 0;

+}
+#endif



+#ifndef __UBOOT__
+static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
+#else
+void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
+#endif
+{

u32			reg;

/* enable all IRQs */
reg = USBOTGSS_IRQO_COREIRQ_ST;
dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);

reg = (USBOTGSS_IRQ1_OEVT |
	USBOTGSS_IRQ1_DRVVBUS_RISE |


	USBOTGSS_IRQ1_CHRGVBUS_RISE |


	USBOTGSS_IRQ1_DISCHRGVBUS_RISE |


	USBOTGSS_IRQ1_IDPULLUP_RISE |


	USBOTGSS_IRQ1_DRVVBUS_FALL |


	USBOTGSS_IRQ1_CHRGVBUS_FALL |


	USBOTGSS_IRQ1_DISCHRGVBUS_FALL |


	USBOTGSS_IRQ1_IDPULLUP_FALL);



dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);

+}



+static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
+{

/* disable all IRQs */
dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, 0x00);
dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, 0x00);

+}
+#ifndef __UBOOT__
+static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);



+static int dwc3_omap_probe(struct platform_device *pdev)
+{

struct device_node	*node = pdev->dev.of_node;

struct dwc3_omap	*omap;
struct resource		*res;
struct device		*dev = &pdev->dev;

int			ret = -ENOMEM;
int			irq;

int			utmi_mode = 0;

u32			reg;

void __iomem		*base;

if (!node) {
dev_err(dev, "device node not found\n");


return -EINVAL;


}

omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
if (!omap) {
dev_err(dev, "not enough memory\n");


return -ENOMEM;


}

platform_set_drvdata(pdev, omap);

irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(dev, "missing IRQ resource\n");


return -EINVAL;


}

res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(dev, "missing memory base resource\n");


return -EINVAL;


}

base = devm_ioremap_nocache(dev, res->start, resource_size(res));
if (!base) {
dev_err(dev, "ioremap failed\n");


return -ENOMEM;


}

spin_lock_init(&omap->lock);

omap->dev	= dev;
omap->irq	= irq;
omap->base	= base;
dev->dma_mask	= &dwc3_omap_dma_mask;

/*
* REVISIT if we ever have two instances of the wrapper, we will be


* in big trouble


*/


_omap	= omap;

pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
dev_err(dev, "get_sync failed with err %d\n", ret);


return ret;


}

reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);

of_property_read_u32(node, "utmi-mode", &utmi_mode);

switch (utmi_mode) {
case DWC3_OMAP_UTMI_MODE_SW:
reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;


break;


case DWC3_OMAP_UTMI_MODE_HW:
reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;


break;


default:
dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);


}

dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);

/* check the DMA Status */
reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);

ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
	"dwc3-omap", omap);


if (ret) {
dev_err(dev, "failed to request IRQ #%d --> %d\n",


		omap->irq, ret);


return ret;


}

dwc3_omap_enable_irqs(omap);

ret = of_platform_populate(node, NULL, NULL, dev);
if (ret) {
dev_err(&pdev->dev, "failed to create dwc3 core\n");


return ret;


}

return 0;

+}



+static int dwc3_omap_remove(struct platform_device *pdev)
+{

struct dwc3_omap	*omap = platform_get_drvdata(pdev);

dwc3_omap_disable_irqs(omap);
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);

return 0;

+}



+static const struct of_device_id of_dwc3_match[] = {

{
.compatible =	"ti,dwc3"


},
{ },

+};
+MODULE_DEVICE_TABLE(of, of_dwc3_match);



+#ifdef CONFIG_PM_SLEEP
+static int dwc3_omap_prepare(struct device *dev)
+{

struct dwc3_omap	*omap = dev_get_drvdata(dev);

dwc3_omap_disable_irqs(omap);

return 0;

+}



+static void dwc3_omap_complete(struct device *dev)
+{

struct dwc3_omap	*omap = dev_get_drvdata(dev);

dwc3_omap_enable_irqs(omap);

+}



+static int dwc3_omap_suspend(struct device *dev)
+{

struct dwc3_omap	*omap = dev_get_drvdata(dev);

omap->utmi_otg_status = dwc3_omap_readl(omap->base,
	USBOTGSS_UTMI_OTG_STATUS);



return 0;

+}



+static int dwc3_omap_resume(struct device *dev)
+{

struct dwc3_omap	*omap = dev_get_drvdata(dev);

dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS,
	omap->utmi_otg_status);



pm_runtime_disable(dev);
pm_runtime_set_active(dev);
pm_runtime_enable(dev);

return 0;

+}



+static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {

.prepare	= dwc3_omap_prepare,
.complete	= dwc3_omap_complete,

SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)

+};



+#define DEV_PM_OPS	(&dwc3_omap_dev_pm_ops)
+#else
+#define DEV_PM_OPS	NULL
+#endif /* CONFIG_PM_SLEEP */



+static struct platform_driver dwc3_omap_driver = {

.probe		= dwc3_omap_probe,
.remove		= dwc3_omap_remove,
.driver		= {
.name	= "omap-dwc3",


.of_match_table	= of_dwc3_match,


.pm	= DEV_PM_OPS,


},

+};



+module_platform_driver(dwc3_omap_driver);
+#endif /* __UBOOT__ */



+MODULE_ALIAS("platform:omap-dwc3");
+MODULE_AUTHOR("Felipe Balbi balbi@ti.com");
+MODULE_LICENSE("Dual BSD/GPL");
+MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");
diff --git a/drivers/usb/dwc3/dwc3-omap.h b/drivers/usb/dwc3/dwc3-omap.h
new file mode 100644
index 0000000..e80a89f
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-omap.h
@@ -0,0 +1,41 @@
+/*


Copyright (C) 2013 by Texas Instruments










Back-ported by: Dan Murphy dmurphy@ti.com







The Inventra Controller Driver for Linux is free software; you



can redistribute it and/or modify it under the terms of the GNU



General Public License version 2 as published by the Free Software



Foundation.


*/


+#ifndef __DWC3_OMAP_H__
+#define __DWC3_OMAP_H__



+enum omap_dwc3_vbus_id_status {

OMAP_DWC3_UNKNOWN = 0,
OMAP_DWC3_ID_GROUND,
OMAP_DWC3_ID_FLOAT,
OMAP_DWC3_VBUS_VALID,
OMAP_DWC3_VBUS_OFF,

+};



+enum dwc3_omap_utmi_mode {

DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
DWC3_OMAP_UTMI_MODE_HW,
DWC3_OMAP_UTMI_MODE_SW,

+};



+#if defined(CONFIG_USB_DWC3)
+extern int dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status);
+#endif
+/*
+TODO need this override for non-USB_DWC3
+#else
+static inline int dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
+{

return -ENODEV;

+}
+#endif
+*/
+#endif	/* __DWC3_OMAP_H__ */
diff --git a/drivers/usb/dwc3/dwc3-uboot.c b/drivers/usb/dwc3/dwc3-uboot.c
new file mode 100644
index 0000000..3732462
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-uboot.c
@@ -0,0 +1,384 @@
+/**


dwc3-uboot.c - dwc3 uboot initialization







Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com







Authors: Dan Murphy dmurphy@ti.com







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions, and the following disclaimer,



without modification.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




The names of the above-listed copyright holders may not be used





to endorse or promote products derived from this software without



specific prior written permission.







ALTERNATIVELY, this software may be distributed under the terms of the



GNU General Public License ("GPL") version 2, as published by the Free



Software Foundation.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS



IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,



THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR



PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR



CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,



EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,



PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR



PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF



LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING



NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS



SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


*/


+#include <usb.h>
+#include <linux/usb/linux-compat.h>
+#include <linux/usb/usb-compat.h>
+#include <usb_defs.h>



+#include "core.h"
+#include "io.h"
+#include "dwc3-omap.h"



+#define DWC3_ALIGN_MASK		(16 - 1)



+static char *maximum_speed = "super";




+#include <asm/omap_common.h>
+/* IRQS0 BITS */
+#define USBOTGSS_IRQO_COREIRQ_ST		(1 << 0)



+/* IRQ1 BITS */
+#define USBOTGSS_IRQ1_DMADISABLECLR		(1 << 17)
+#define USBOTGSS_IRQ1_OEVT			(1 << 16)
+#define USBOTGSS_IRQ1_DRVVBUS_RISE		(1 << 13)
+#define USBOTGSS_IRQ1_CHRGVBUS_RISE		(1 << 12)
+#define USBOTGSS_IRQ1_DISCHRGVBUS_RISE		(1 << 11)
+#define USBOTGSS_IRQ1_IDPULLUP_RISE		(1 << 8)
+#define USBOTGSS_IRQ1_DRVVBUS_FALL		(1 << 5)
+#define USBOTGSS_IRQ1_CHRGVBUS_FALL		(1 << 4)
+#define USBOTGSS_IRQ1_DISCHRGVBUS_FALL		(1 << 3)
+#define USBOTGSS_IRQ1_IDPULLUP_FALL		(1 << 0)



+#define USBOTGSS_IRQENABLE_SET_0	0x4A02002c
+#define USBOTGSS_IRQENABLE_SET_1	0x4A02003c
+#define USBOTGSS_SYSCONFIG		0x4A020010
+#define USBOTGSS_IRQSTATUS_0		0x4A020028
+#define USBOTGSS_IRQSTATUS_1		0x4A020038
+#define USBOTGSS_UTMI_OTG_STATUS 0x4A020084



+struct usb_dpll_params {

u16	m;
u8	n;
u8	freq:3;
u8	sd;
u32	mf;

+};



+static struct usb_dpll_params omap_usb3_dpll_params[6] = {

{1250, 5, 4, 20, 0},		/* 12 MHz */
{0, 0, 0, 0, 0},		/* for 13 MHz TBD   */
{3125, 20, 4, 20, 0},		/* 16.8 MHz */
{1172, 8, 4, 20, 65537},	/* 19.2 MHz */
{1250, 12, 4, 20, 0},		/* 26 MHz */
{3125, 47, 4, 20, 92843},	/* 38.4 MHz */

+};



+#define USB3_PHY_PLL_CONFIGURATION1	0x4A084C0C
+#define USB3_PHY_PLL_REGN_MASK		0xFE
+#define USB3_PHY_PLL_REGN_SHIFT		1
+#define USB3_PHY_PLL_REGM_MASK		0x1FFE00
+#define USB3_PHY_PLL_REGM_SHIFT		9
+#define USB3_PHY_PLL_CONFIGURATION2	0x4A084C10
+#define USB3_PHY_PLL_SELFREQDCO_MASK	0xE
+#define USB3_PHY_PLL_SELFREQDCO_SHIFT	1
+#define USB3_PHY_PLL_CONFIGURATION4     0x4A084C20
+#define USB3_PHY_PLL_REGM_F_MASK	0x3FFFF
+#define USB3_PHY_PLL_REGM_F_SHIFT	0
+#define USB3_PHY_PLL_CONFIGURATION3	0x4A084C14
+#define USB3_PHY_PLL_SD_MASK		0x3FC00
+#define USB3_PHY_PLL_SD_SHIFT		9
+#define USB3_PHY_CONTROL_PHY_POWER_USB	0x4A002370
+#define USB3_PWRCTL_CLK_CMD_MASK	0x3FE000
+#define USB3_PWRCTL_CLK_FREQ_MASK	0xFFC
+#define USB3_PHY_PARTIAL_RX_POWERON     (1<<6)
+#define USB3_PHY_TX_RX_POWERON		0x3
+#define USB3_PWRCTL_CLK_CMD_SHIFT	14
+#define USB3_PWRCTL_CLK_FREQ_SHIFT	22
+#define USB3_PHY_PLL_IDLE		1



+#define USB3_PHY_PLL_STATUS	0x4A084C04
+#define USB3_PHY_PLL_TICOPWDN   0x10000
+#define USB3_PHY_PLL_LOCK	0x2
+#define CONTROL_DEV_CONF	0x4A002300
+#define CONTROL_DEV_CONF_USBPHY_PD	1



+#define USB3_PHY_PLL_GO		0x4A084C08
+#define USB3_PHY_SET_PLL_GO	1



+void setup_usb(void)
+{

u32			val;
u32			retry;
u8 vali;
writel(0x118, 0x4A0029EC);
writel(0x1180000, 0x4A0029F0);
writel(0x118, 0x4A0029F4);
/* Turn on 32K AON clk */
writel(0x100, 0x4A008640);
/* Setting USBOTGSS_SYSCONFIG set to NO idle  */
val = readl(0x4A020010);
writel(0x10034, 0x4A020010);

/* Set the IRQ Enables */
/* Clear status */
val = readl(USBOTGSS_UTMI_OTG_STATUS);
writel(val, USBOTGSS_UTMI_OTG_STATUS);
/* Enable interrupts */
writel(0x1, USBOTGSS_IRQENABLE_SET_0);
writel(0x13939, USBOTGSS_IRQENABLE_SET_1);
/* Check for non zero status */
val = readl(USBOTGSS_IRQSTATUS_1);
writel(val, USBOTGSS_IRQSTATUS_1);
val = readl(USBOTGSS_IRQSTATUS_0);
writel(val, USBOTGSS_IRQSTATUS_0);

+}



+#ifdef CONFIG_USB_DWC3_HOST
+static struct musb *host;
+static struct usb_hcd hcd;
+static enum usb_device_speed host_speed;



+#define DWC_HOST_TIMEOUT	0x3ffffff



+static struct usb_host_endpoint hep;
+static struct urb urb;



+static void dwc3_host_complete_urb(struct urb *urb)
+{

urb->dev->status &= ~USB_ST_NOT_PROC;
urb->dev->act_len = urb->actual_length;

return;

+}



+static struct urb *construct_urb(struct usb_device *dev, int endpoint_type,

		unsigned long pipe, void *buffer, int len,


		struct devrequest *setup, int interval)



+{

int epnum = usb_pipeendpoint(pipe);
int is_in = usb_pipein(pipe);

memset(&urb, 0, sizeof(struct urb));
memset(&hep, 0, sizeof(struct usb_host_endpoint));

INIT_LIST_HEAD(&hep.urb_list);

INIT_LIST_HEAD(&urb.urb_list);
urb.ep = &hep;
urb.complete = dwc3_host_complete_urb;
urb.status = -EINPROGRESS;
urb.dev = dev;
urb.pipe = pipe;
urb.transfer_buffer = buffer;
urb.transfer_dma = (unsigned long)buffer;
urb.transfer_buffer_length = len;
urb.setup_packet = (unsigned char *)setup;

urb.ep->desc.wMaxPacketSize =
__cpu_to_le16(is_in ? dev->epmaxpacketin[epnum] :


		dev->epmaxpacketout[epnum]);


urb.ep->desc.bmAttributes = endpoint_type;
urb.ep->desc.bEndpointAddress =
(is_in ? USB_DIR_IN : USB_DIR_OUT) | epnum;


urb.ep->desc.bInterval = interval;

return &urb;

+}



+static int submit_urb(struct usb_hcd *hcd, struct urb *urb)
+{

return NULL;

+}



+int submit_control_msg(struct usb_device *dev, unsigned long pipe,

	void *buffer, int len, struct devrequest *setup)



+{

struct urb *urb = construct_urb(dev, USB_ENDPOINT_XFER_CONTROL, pipe,
			buffer, len, setup, 0);



/* Fix speed for non hub-attached devices */
if (!dev->parent)
dev->speed = host_speed;



return submit_urb(&hcd, urb);

+}




+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,

			void *buffer, int len)



+{

struct urb *urb = construct_urb(dev, USB_ENDPOINT_XFER_BULK, pipe,
			buffer, len, NULL, 0);


return submit_urb(&hcd, urb);

+}



+int submit_int_msg(struct usb_device *dev, unsigned long pipe,

		void *buffer, int len, int interval)



+{

struct urb *urb = construct_urb(dev, USB_ENDPOINT_XFER_INT, pipe,
			buffer, len, NULL, interval);


return submit_urb(&hcd, urb);

+}



+/* The init sequence was abstracted from the core.c probe function */
+int usb_lowlevel_init(int index, void **controller)
+{

struct dwc3 *dwc;
int ret = -ENOMEM;
void *mem;
u8 mode;

mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
if (!mem) {
dev_err(dev, "not enough memory\n");


return -ENOMEM;


}
dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
dwc->mem = mem;
dwc->regs = 0x4A030000;

if (!strncmp("super", maximum_speed, 5))
dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;


else if (!strncmp("high", maximum_speed, 4))
dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;


else if (!strncmp("full", maximum_speed, 4))
dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;


else if (!strncmp("low", maximum_speed, 3))
dwc->maximum_speed = DWC3_DCFG_LOWSPEED;


else
dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;



setup_usb();

dwc3_cache_hwparams(dwc);

ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
if (ret) {
dev_err(dwc->dev, "failed to allocate event buffers\n");


ret = -ENOMEM;


goto err0;


}

ret = dwc3_core_init(dwc);
if (ret) {
dev_err(dev, "failed to initialize core\n");


goto err0;


}

ret = dwc3_event_buffers_setup(dwc);
if (ret) {
dev_err(dwc->dev, "failed to setup event buffers\n");


goto err1;


}

+/* TODO: Figure out how to enable this

if (CONFIG_USB_DWC3_HOST)
mode = DWC3_MODE_HOST;


else if (CONFIG_USB_DWC3_GADGET)
mode = DWC3_MODE_DEVICE;


else
mode = DWC3_MODE_DRD;



+*/

mode = DWC3_MODE_HOST;
switch (mode) {
case DWC3_MODE_DEVICE:
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);


ret = dwc3_gadget_init(dwc);


if (ret) {


	printf("failed to initialize gadget\n");


	goto err2;


}


break;


case DWC3_MODE_HOST:
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);


ret = dwc3_host_init(dwc);


if (ret) {


	printf("failed to initialize host\n");


	goto err2;


}


break;


case DWC3_MODE_DRD:
dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);


ret = dwc3_host_init(dwc);


if (ret) {


	printf("failed to initialize host\n");


	goto err2;


}



ret = dwc3_gadget_init(dwc);


if (ret) {


	printf("failed to initialize gadget\n");


	goto err2;


}


break;


default:
printf("Unsupported mode of operation %d\n", mode);


goto err2;


}
dwc->mode = mode;

return 0;


+err2:

dwc3_event_buffers_cleanup(dwc);


+err1:

dwc3_core_exit(dwc);


+err0:

dwc3_free_event_buffers(dwc);

return ret;

+}



+int usb_lowlevel_stop(int index)
+{

return 0;

+}
+#endif /* CONFIG_USB_DWC3_HOST */



+#ifdef CONFIG_USB_DWC3_GADGET
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{

return 0;

+}



+static struct dwc *gadget;
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{

int ret;

if (!driver || /* driver->speed < USB_SPEED_FULL ||*/ !driver->bind ||
   !driver->setup) {


printf("bad parameter.\n");


return -EINVAL;


}

if (!gadget) {
printf("Controller uninitialized\n");


return -ENXIO;


}

return 0;

+}



+int usb_gadget_handle_interrupts(void)
+{

return 0;

+}
+#endif /* CONFIG_USB_DWC3_GADGET */
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
new file mode 100644
index 0000000..3bdc6e6
--- /dev/null
+++ b/drivers/usb/dwc3/ep0.c
@@ -0,0 +1,1085 @@
+/**


ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling







Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com







Authors: Felipe Balbi balbi@ti.com,



   Sebastian Andrzej Siewior <bigeasy@linutronix.de>









Back-ported by: Dan Murphy dmurphy@ti.com







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions, and the following disclaimer,



without modification.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




The names of the above-listed copyright holders may not be used





to endorse or promote products derived from this software without



specific prior written permission.







ALTERNATIVELY, this software may be distributed under the terms of the



GNU General Public License ("GPL") version 2, as published by the Free



Software Foundation.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS



IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,



THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR



PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR



CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,



EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,



PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR



PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF



LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING



NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS



SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


*/


+#define __UBOOT__
+#ifndef __UBOOT__
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/dma-mapping.h>



+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#else



+#include <common.h>



+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#include <linux/usb/linux-compat.h>
+#include <usb/lin_gadget_compat.h>



+#endif
+#include "core.h"
+#include "gadget.h"
+#include "io.h"



+static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
+static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,

struct dwc3_ep *dep, struct dwc3_request *req);




+static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
+{

switch (state) {
case EP0_UNCONNECTED:
return "Unconnected";


case EP0_SETUP_PHASE:
return "Setup Phase";


case EP0_DATA_PHASE:
return "Data Phase";


case EP0_STATUS_PHASE:
return "Status Phase";


default:
return "UNKNOWN";


}

+}



+static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,

u32 len, u32 type)



+{

struct dwc3_gadget_ep_cmd_params params;
struct dwc3_trb			*trb;
struct dwc3_ep			*dep;

int				ret;

dep = dwc->eps[epnum];
if (dep->flags & DWC3_EP_BUSY) {
dev_vdbg(dwc->dev, "%s: still busy\n", dep->name);


return 0;


}

trb = dwc->ep0_trb;

trb->bpl = lower_32_bits(buf_dma);
trb->bph = upper_32_bits(buf_dma);
trb->size = len;
trb->ctrl = type;

trb->ctrl |= (DWC3_TRB_CTRL_HWO
	| DWC3_TRB_CTRL_LST


	| DWC3_TRB_CTRL_IOC


	| DWC3_TRB_CTRL_ISP_IMI);



memset(&params, 0, sizeof(params));
params.param0 = upper_32_bits(dwc->ep0_trb_addr);
params.param1 = lower_32_bits(dwc->ep0_trb_addr);

ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
	DWC3_DEPCMD_STARTTRANSFER, &params);


if (ret < 0) {
dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");


return ret;


}

dep->flags |= DWC3_EP_BUSY;
dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
	dep->number);



dwc->ep0_next_event = DWC3_EP0_COMPLETE;

return 0;

+}



+static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,

struct dwc3_request *req)



+{

struct dwc3		*dwc = dep->dwc;

req->request.actual	= 0;
req->request.status	= -EINPROGRESS;
req->epnum		= dep->number;

list_add_tail(&req->list, &dep->request_list);

/*
* Gadget driver might not be quick enough to queue a request


* before we get a Transfer Not Ready event on this endpoint.


*


* In that case, we will set DWC3_EP_PENDING_REQUEST. When that


* flag is set, it's telling us that as soon as Gadget queues the


* required request, we should kick the transfer here because the


* IRQ we were waiting for is long gone.


*/


if (dep->flags & DWC3_EP_PENDING_REQUEST) {
unsigned	direction;



direction = !!(dep->flags & DWC3_EP0_DIR_IN);



if (dwc->ep0state != EP0_DATA_PHASE) {



+#ifndef __UBOOT__

	dev_WARN(dwc->dev, "Unexpected pending request\n");



+#else

	printf("Unexpected pending request\n");



+#endif

	return 0;


}



__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);



dep->flags &= ~(DWC3_EP_PENDING_REQUEST |


		DWC3_EP0_DIR_IN);



return 0;


}

/*
* In case gadget driver asked us to delay the STATUS phase,


* handle it here.


*/


if (dwc->delayed_status) {
unsigned	direction;



direction = !dwc->ep0_expect_in;


dwc->delayed_status = false;



if (dwc->ep0state == EP0_STATUS_PHASE)


	__dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);


else


	dev_dbg(dwc->dev, "too early for delayed status\n");



return 0;


}

/*
* Unfortunately we have uncovered a limitation wrt the Data Phase.


*


* Section 9.4 says we can wait for the XferNotReady(DATA) event to


* come before issueing Start Transfer command, but if we do, we will


* miss situations where the host starts another SETUP phase instead of


* the DATA phase.  Such cases happen at least on TD.7.6 of the Link


* Layer Compliance Suite.


*


* The problem surfaces due to the fact that in case of back-to-back


* SETUP packets there will be no XferNotReady(DATA) generated and we


* will be stuck waiting for XferNotReady(DATA) forever.


*


* By looking at tables 9-13 and 9-14 of the Databook, we can see that


* it tells us to start Data Phase right away. It also mentions that if


* we receive a SETUP phase instead of the DATA phase, core will issue


* XferComplete for the DATA phase, before actually initiating it in


* the wire, with the TRB's status set to "SETUP_PENDING". Such status


* can only be used to print some debugging logs, as the core expects


* us to go through to the STATUS phase and start a CONTROL_STATUS TRB,


* just so it completes right away, without transferring anything and,


* only then, we can go back to the SETUP phase.


*


* Because of this scenario, SNPS decided to change the programming


* model of control transfers and support on-demand transfers only for


* the STATUS phase. To fix the issue we have now, we will always wait


* for gadget driver to queue the DATA phase's struct usb_request, then


* start it right away.


*


* If we're actually in a 2-stage transfer, we will wait for


* XferNotReady(STATUS).


*/


if (dwc->three_stage_setup) {
unsigned        direction;



direction = dwc->ep0_expect_in;


dwc->ep0state = EP0_DATA_PHASE;



__dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);



dep->flags &= ~DWC3_EP0_DIR_IN;


}

return 0;

+}



+int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,

gfp_t gfp_flags)



+{

struct dwc3_request		*req = to_dwc3_request(request);
struct dwc3_ep			*dep = to_dwc3_ep(ep);
struct dwc3			*dwc = dep->dwc;

unsigned long			flags;

int				ret;

spin_lock_irqsave(&dwc->lock, flags);
if (!dep->endpoint.desc) {
dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",


		request, dep->name);


ret = -ESHUTDOWN;


goto out;


}

/* we share one TRB for ep0/1 */
if (!list_empty(&dep->request_list)) {
ret = -EBUSY;


goto out;


}

dev_vdbg(dwc->dev, "queueing request %p to %s length %d, state '%s'\n",
	request, dep->name, request->length,


	dwc3_ep0_state_string(dwc->ep0state));



ret = __dwc3_gadget_ep0_queue(dep, req);


+out:

spin_unlock_irqrestore(&dwc->lock, flags);

return ret;

+}



+static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
+{

struct dwc3_ep		*dep;

/* reinitialize physical ep1 */
dep = dwc->eps[1];
dep->flags = DWC3_EP_ENABLED;

/* stall is always issued on EP0 */
dep = dwc->eps[0];
__dwc3_gadget_ep_set_halt(dep, 1);
dep->flags = DWC3_EP_ENABLED;
dwc->delayed_status = false;

if (!list_empty(&dep->request_list)) {
struct dwc3_request	*req;



req = next_request(&dep->request_list);


dwc3_gadget_giveback(dep, req, -ECONNRESET);


}

dwc->ep0state = EP0_SETUP_PHASE;
dwc3_ep0_out_start(dwc);

+}



+int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
+{

struct dwc3_ep			*dep = to_dwc3_ep(ep);
struct dwc3			*dwc = dep->dwc;

dwc3_ep0_stall_and_restart(dwc);

return 0;

+}



+void dwc3_ep0_out_start(struct dwc3 *dwc)
+{

int				ret;

ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
	DWC3_TRBCTL_CONTROL_SETUP);


WARN_ON(ret < 0);

+}



+static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
+{

struct dwc3_ep		*dep;
u32			windex = le16_to_cpu(wIndex_le);
u32			epnum;

epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
epnum |= 1;



dep = dwc->eps[epnum];
if (dep->flags & DWC3_EP_ENABLED)
return dep;



return NULL;

+}



+static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
+{
+}
+/*


ch 9.4.5


*/

+static int dwc3_ep0_handle_status(struct dwc3 *dwc,

struct usb_ctrlrequest *ctrl)



+{

struct dwc3_ep		*dep;
u32			recip;
u32			reg;
u16			usb_status = 0;
__le16			*response_pkt;

recip = ctrl->bRequestType & USB_RECIP_MASK;
switch (recip) {
case USB_RECIP_DEVICE:
/*


 * LTM will be set once we know how to set this in HW.


 */


usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;



if (dwc->speed == DWC3_DSTS_SUPERSPEED) {


	reg = dwc3_readl(dwc->regs, DWC3_DCTL);


	if (reg & DWC3_DCTL_INITU1ENA)


		usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;


	if (reg & DWC3_DCTL_INITU2ENA)


		usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;


}



break;



case USB_RECIP_INTERFACE:
/*


 * Function Remote Wake Capable	D0


 * Function Remote Wakeup	D1


 */


break;



case USB_RECIP_ENDPOINT:
dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);


if (!dep)


	return -EINVAL;



if (dep->flags & DWC3_EP_STALL)


	usb_status = 1 << USB_ENDPOINT_HALT;


break;


default:
return -EINVAL;


};

response_pkt = (__le16 *) dwc->setup_buf;
*response_pkt = cpu_to_le16(usb_status);

dep = dwc->eps[0];
dwc->ep0_usb_req.dep = dep;
dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
dwc->ep0_usb_req.request.buf = dwc->setup_buf;
dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;

return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);

+}



+static int dwc3_ep0_handle_feature(struct dwc3 *dwc,

struct usb_ctrlrequest *ctrl, int set)



+{

struct dwc3_ep		*dep;
u32			recip;
u32			wValue;
u32			wIndex;
u32			reg;
int			ret;
enum usb_device_state	state;

wValue = le16_to_cpu(ctrl->wValue);
wIndex = le16_to_cpu(ctrl->wIndex);
recip = ctrl->bRequestType & USB_RECIP_MASK;
state = dwc->gadget.state;

switch (recip) {
case USB_RECIP_DEVICE:

switch (wValue) {


case USB_DEVICE_REMOTE_WAKEUP:


	break;


/*


 * 9.4.1 says only only for SS, in AddressState only for


 * default control pipe


 */


case USB_DEVICE_U1_ENABLE:


	if (state != USB_STATE_CONFIGURED)


		return -EINVAL;


	if (dwc->speed != DWC3_DSTS_SUPERSPEED)


		return -EINVAL;



	reg = dwc3_readl(dwc->regs, DWC3_DCTL);


	if (set)


		reg |= DWC3_DCTL_INITU1ENA;


	else


		reg &= ~DWC3_DCTL_INITU1ENA;


	dwc3_writel(dwc->regs, DWC3_DCTL, reg);


	break;



case USB_DEVICE_U2_ENABLE:


	if (state != USB_STATE_CONFIGURED)


		return -EINVAL;


	if (dwc->speed != DWC3_DSTS_SUPERSPEED)


		return -EINVAL;



	reg = dwc3_readl(dwc->regs, DWC3_DCTL);


	if (set)


		reg |= DWC3_DCTL_INITU2ENA;


	else


		reg &= ~DWC3_DCTL_INITU2ENA;


	dwc3_writel(dwc->regs, DWC3_DCTL, reg);


	break;



case USB_DEVICE_LTM_ENABLE:


	return -EINVAL;


	break;



case USB_DEVICE_TEST_MODE:


	if ((wIndex & 0xff) != 0)


		return -EINVAL;


	if (!set)


		return -EINVAL;



	dwc->test_mode_nr = wIndex >> 8;


	dwc->test_mode = true;


	break;


default:


	return -EINVAL;


}


break;



case USB_RECIP_INTERFACE:
switch (wValue) {


case USB_INTRF_FUNC_SUSPEND:


	if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)


		/* XXX enable Low power suspend */


		;


	if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)


		/* XXX enable remote wakeup */


		;


	break;


default:


	return -EINVAL;


}


break;



case USB_RECIP_ENDPOINT:
switch (wValue) {


case USB_ENDPOINT_HALT:


	dep = dwc3_wIndex_to_dep(dwc, wIndex);


	if (!dep)


		return -EINVAL;


	ret = __dwc3_gadget_ep_set_halt(dep, set);


	if (ret)


		return -EINVAL;


	break;


default:


	return -EINVAL;


}


break;



default:
return -EINVAL;


};

return 0;

+}



+static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
+{

enum usb_device_state state = dwc->gadget.state;
u32 addr;
u32 reg;

addr = le16_to_cpu(ctrl->wValue);
if (addr > 127) {
dev_dbg(dwc->dev, "invalid device address %d\n", addr);


return -EINVAL;


}

if (state == USB_STATE_CONFIGURED) {
dev_dbg(dwc->dev, "trying to set address when configured\n");


return -EINVAL;


}

reg = dwc3_readl(dwc->regs, DWC3_DCFG);
reg &= ~(DWC3_DCFG_DEVADDR_MASK);
reg |= DWC3_DCFG_DEVADDR(addr);
dwc3_writel(dwc->regs, DWC3_DCFG, reg);

if (addr)
usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);


else
usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);



return 0;

+}



+static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
+{

int ret;

spin_unlock(&dwc->lock);
ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
spin_lock(&dwc->lock);
return ret;

+}



+static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
+{

enum usb_device_state state = dwc->gadget.state;
u32 cfg;
int ret;
u32 reg;

dwc->start_config_issued = false;
cfg = le16_to_cpu(ctrl->wValue);

switch (state) {
case USB_STATE_DEFAULT:
return -EINVAL;


break;



case USB_STATE_ADDRESS:
ret = dwc3_ep0_delegate_req(dwc, ctrl);


/* if the cfg matches and the cfg is non zero */


if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {


	usb_gadget_set_state(&dwc->gadget,


			USB_STATE_CONFIGURED);



	/*


	 * Enable transition to U1/U2 state when


	 * nothing is pending from application.


	 */


	reg = dwc3_readl(dwc->regs, DWC3_DCTL);


	reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);


	dwc3_writel(dwc->regs, DWC3_DCTL, reg);



	dwc->resize_fifos = true;


	dev_dbg(dwc->dev, "resize fifos flag SET\n");


}


break;



case USB_STATE_CONFIGURED:
ret = dwc3_ep0_delegate_req(dwc, ctrl);


if (!cfg)


	usb_gadget_set_state(&dwc->gadget,


			USB_STATE_ADDRESS);


break;


default:
ret = -EINVAL;


}
return ret;

+}



+static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
+{

struct dwc3_ep	*dep = to_dwc3_ep(ep);
struct dwc3	*dwc = dep->dwc;

u32		param = 0;
u32		reg;

struct timing {
u8	u1sel;


u8	u1pel;


u16	u2sel;


u16	u2pel;


} __packed timing;

int		ret;

memcpy(&timing, req->buf, sizeof(timing));

dwc->u1sel = timing.u1sel;
dwc->u1pel = timing.u1pel;
dwc->u2sel = le16_to_cpu(timing.u2sel);
dwc->u2pel = le16_to_cpu(timing.u2pel);

reg = dwc3_readl(dwc->regs, DWC3_DCTL);
if (reg & DWC3_DCTL_INITU2ENA)
param = dwc->u2pel;


if (reg & DWC3_DCTL_INITU1ENA)
param = dwc->u1pel;



/*
* According to Synopsys Databook, if parameter is


* greater than 125, a value of zero should be


* programmed in the register.


*/


if (param > 125)
param = 0;



/* now that we have the time, issue DGCMD Set Sel */
ret = dwc3_send_gadget_generic_command(dwc,
	DWC3_DGCMD_SET_PERIODIC_PAR, param);


WARN_ON(ret < 0);

+}



+static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
+{

struct dwc3_ep	*dep;
enum usb_device_state state = dwc->gadget.state;
u16		wLength;
u16		wValue;

if (state == USB_STATE_DEFAULT)
return -EINVAL;



wValue = le16_to_cpu(ctrl->wValue);
wLength = le16_to_cpu(ctrl->wLength);

if (wLength != 6) {
dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",


		wLength);


return -EINVAL;


}

/*
* To handle Set SEL we need to receive 6 bytes from Host. So let's


* queue a usb_request for 6 bytes.


*


* Remember, though, this controller can't handle non-wMaxPacketSize


* aligned transfers on the OUT direction, so we queue a request for


* wMaxPacketSize instead.


*/


dep = dwc->eps[0];
dwc->ep0_usb_req.dep = dep;
dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
dwc->ep0_usb_req.request.buf = dwc->setup_buf;
dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;

return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);

+}



+static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
+{

u16		wLength;
u16		wValue;
u16		wIndex;

wValue = le16_to_cpu(ctrl->wValue);
wLength = le16_to_cpu(ctrl->wLength);
wIndex = le16_to_cpu(ctrl->wIndex);

if (wIndex || wLength)
return -EINVAL;



/*
* REVISIT It's unclear from Databook what to do with this


* value. For now, just cache it.


*/


dwc->isoch_delay = wValue;

return 0;

+}



+static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
+{

int ret;

switch (ctrl->bRequest) {
case USB_REQ_GET_STATUS:
dev_vdbg(dwc->dev, "USB_REQ_GET_STATUS\n");


ret = dwc3_ep0_handle_status(dwc, ctrl);


break;


case USB_REQ_CLEAR_FEATURE:
dev_vdbg(dwc->dev, "USB_REQ_CLEAR_FEATURE\n");


ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);


break;


case USB_REQ_SET_FEATURE:
dev_vdbg(dwc->dev, "USB_REQ_SET_FEATURE\n");


ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);


break;


case USB_REQ_SET_ADDRESS:
dev_vdbg(dwc->dev, "USB_REQ_SET_ADDRESS\n");


ret = dwc3_ep0_set_address(dwc, ctrl);


break;


case USB_REQ_SET_CONFIGURATION:
dev_vdbg(dwc->dev, "USB_REQ_SET_CONFIGURATION\n");


ret = dwc3_ep0_set_config(dwc, ctrl);


break;


case USB_REQ_SET_SEL:
dev_vdbg(dwc->dev, "USB_REQ_SET_SEL\n");


ret = dwc3_ep0_set_sel(dwc, ctrl);


break;


case USB_REQ_SET_ISOCH_DELAY:
dev_vdbg(dwc->dev, "USB_REQ_SET_ISOCH_DELAY\n");


ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);


break;


default:
dev_vdbg(dwc->dev, "Forwarding to gadget driver\n");


ret = dwc3_ep0_delegate_req(dwc, ctrl);


break;


};

return ret;

+}



+static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,

const struct dwc3_event_depevt *event)



+{

struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
int ret = -EINVAL;
u32 len;

if (!dwc->gadget_driver)
goto out;



len = le16_to_cpu(ctrl->wLength);
if (!len) {
dwc->three_stage_setup = false;


dwc->ep0_expect_in = false;


dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;


} else {
dwc->three_stage_setup = true;


dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);


dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;


}

if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
ret = dwc3_ep0_std_request(dwc, ctrl);


else
ret = dwc3_ep0_delegate_req(dwc, ctrl);



if (ret == USB_GADGET_DELAYED_STATUS)
dwc->delayed_status = true;




+out:

if (ret < 0)
dwc3_ep0_stall_and_restart(dwc);



+}



+static void dwc3_ep0_complete_data(struct dwc3 *dwc,

const struct dwc3_event_depevt *event)



+{

struct dwc3_request	*r = NULL;
struct usb_request	*ur;
struct dwc3_trb		*trb;
struct dwc3_ep		*ep0;
u32			transferred;
u32			status;
u32			length;
u8			epnum;

epnum = event->endpoint_number;
ep0 = dwc->eps[0];

dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;

r = next_request(&ep0->request_list);
ur = &r->request;

trb = dwc->ep0_trb;

status = DWC3_TRB_SIZE_TRBSTS(trb->size);
if (status == DWC3_TRBSTS_SETUP_PENDING) {
dev_dbg(dwc->dev, "Setup Pending received\n");



if (r)


	dwc3_gadget_giveback(ep0, r, -ECONNRESET);



return;


}

length = trb->size & DWC3_TRB_SIZE_MASK;

if (dwc->ep0_bounced) {
unsigned transfer_size = ur->length;


unsigned maxp = ep0->endpoint.maxpacket;



transfer_size += (maxp - (transfer_size % maxp));


transferred = min_t(u32, ur->length,


		transfer_size - length);


memcpy(ur->buf, dwc->ep0_bounce, transferred);


} else {
transferred = ur->length - length;


}

ur->actual += transferred;

if ((epnum & 1) && ur->actual < ur->length) {
/* for some reason we did not get everything out */



dwc3_ep0_stall_and_restart(dwc);


} else {
/*


 * handle the case where we have to send a zero packet. This


 * seems to be case when req.length > maxpacket. Could it be?


 */


if (r)


	dwc3_gadget_giveback(ep0, r, 0);


}

+}



+static void dwc3_ep0_complete_status(struct dwc3 *dwc,

const struct dwc3_event_depevt *event)



+{

struct dwc3_request	*r;
struct dwc3_ep		*dep;
struct dwc3_trb		*trb;
u32			status;

dep = dwc->eps[0];
trb = dwc->ep0_trb;

if (!list_empty(&dep->request_list)) {
r = next_request(&dep->request_list);



dwc3_gadget_giveback(dep, r, 0);


}

if (dwc->test_mode) {
int ret;



ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);


if (ret < 0) {


	dev_dbg(dwc->dev, "Invalid Test #%d\n",


			dwc->test_mode_nr);


	dwc3_ep0_stall_and_restart(dwc);


	return;


}


}

status = DWC3_TRB_SIZE_TRBSTS(trb->size);
if (status == DWC3_TRBSTS_SETUP_PENDING)
dev_dbg(dwc->dev, "Setup Pending received\n");



dwc->ep0state = EP0_SETUP_PHASE;
dwc3_ep0_out_start(dwc);

+}



+static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,

	const struct dwc3_event_depevt *event)



+{

struct dwc3_ep		*dep = dwc->eps[event->endpoint_number];

dep->flags &= ~DWC3_EP_BUSY;
dep->resource_index = 0;
dwc->setup_packet_pending = false;

switch (dwc->ep0state) {
case EP0_SETUP_PHASE:
dev_vdbg(dwc->dev, "Inspecting Setup Bytes\n");


dwc3_ep0_inspect_setup(dwc, event);


break;



case EP0_DATA_PHASE:
dev_vdbg(dwc->dev, "Data Phase\n");


dwc3_ep0_complete_data(dwc, event);


break;



case EP0_STATUS_PHASE:
dev_vdbg(dwc->dev, "Status Phase\n");


dwc3_ep0_complete_status(dwc, event);


break;


default:
WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);


}

+}



+static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,

struct dwc3_ep *dep, struct dwc3_request *req)



+{

int			ret;

req->direction = !!dep->number;

if (req->request.length == 0) {
ret = dwc3_ep0_start_trans(dwc, dep->number,


		dwc->ctrl_req_addr, 0,


		DWC3_TRBCTL_CONTROL_DATA);


} else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
	&& (dep->number == 0)) {


u32	transfer_size;


u32	maxpacket;



+#ifndef __UBOOT__

/* FIX THIS DM */
ret = usb_gadget_map_request(&dwc->gadget, &req->request,


		dep->number);


if (ret) {


	dev_dbg(dwc->dev, "failed to map request\n");


	return;


}



+#endif

WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);



maxpacket = dep->endpoint.maxpacket;


transfer_size = roundup(req->request.length, maxpacket);



dwc->ep0_bounced = true;



/*


 * REVISIT in case request length is bigger than


 * DWC3_EP0_BOUNCE_SIZE we will need two chained


 * TRBs to handle the transfer.


 */


ret = dwc3_ep0_start_trans(dwc, dep->number,


		dwc->ep0_bounce_addr, transfer_size,


		DWC3_TRBCTL_CONTROL_DATA);


} else {

+#ifndef __UBOOT__

/* FIX THIS DM */
ret = usb_gadget_map_request(&dwc->gadget, &req->request,


		dep->number);


if (ret) {


	dev_dbg(dwc->dev, "failed to map request\n");


	return;


}



+#endif

ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,


		req->request.length, DWC3_TRBCTL_CONTROL_DATA);


}

WARN_ON(ret < 0);

+}



+static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
+{

struct dwc3		*dwc = dep->dwc;
u32			type;

type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
: DWC3_TRBCTL_CONTROL_STATUS2;



return dwc3_ep0_start_trans(dwc, dep->number,
	dwc->ctrl_req_addr, 0, type);



+}



+static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
+{

if (dwc->resize_fifos) {
dev_dbg(dwc->dev, "starting to resize fifos\n");


dwc3_gadget_resize_tx_fifos(dwc);


dwc->resize_fifos = 0;


}

WARN_ON(dwc3_ep0_start_control_status(dep));

+}



+static void dwc3_ep0_do_control_status(struct dwc3 *dwc,

const struct dwc3_event_depevt *event)



+{

struct dwc3_ep		*dep = dwc->eps[event->endpoint_number];

__dwc3_ep0_do_control_status(dwc, dep);

+}



+static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
+{

struct dwc3_gadget_ep_cmd_params params;
u32			cmd;
int			ret;

if (!dep->resource_index)
return;



cmd = DWC3_DEPCMD_ENDTRANSFER;
cmd |= DWC3_DEPCMD_CMDIOC;
cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
memset(&params, 0, sizeof(params));
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
WARN_ON_ONCE(ret);
dep->resource_index = 0;

+}



+static void dwc3_ep0_xfernotready(struct dwc3 *dwc,

const struct dwc3_event_depevt *event)



+{

dwc->setup_packet_pending = true;

switch (event->status) {
case DEPEVT_STATUS_CONTROL_DATA:
dev_vdbg(dwc->dev, "Control Data\n");



/*


 * We already have a DATA transfer in the controller's cache,


 * if we receive a XferNotReady(DATA) we will ignore it, unless


 * it's for the wrong direction.


 *


 * In that case, we must issue END_TRANSFER command to the Data


 * Phase we already have started and issue SetStall on the


 * control endpoint.


 */


if (dwc->ep0_expect_in != event->endpoint_number) {


	struct dwc3_ep	*dep = dwc->eps[dwc->ep0_expect_in];



	dev_vdbg(dwc->dev, "Wrong direction for Data phase\n");


	dwc3_ep0_end_control_data(dwc, dep);


	dwc3_ep0_stall_and_restart(dwc);


	return;


}



break;



case DEPEVT_STATUS_CONTROL_STATUS:
if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)


	return;



dev_vdbg(dwc->dev, "Control Status\n");



dwc->ep0state = EP0_STATUS_PHASE;



if (dwc->delayed_status) {


	WARN_ON_ONCE(event->endpoint_number != 1);


	dev_vdbg(dwc->dev, "Mass Storage delayed status\n");


	return;


}



dwc3_ep0_do_control_status(dwc, event);


}

+}



+void dwc3_ep0_interrupt(struct dwc3 *dwc,

const struct dwc3_event_depevt *event)



+{

u8			epnum = event->endpoint_number;

dev_dbg(dwc->dev, "%s while ep%d%s in state '%s'\n",
	dwc3_ep_event_string(event->endpoint_event),


	epnum >> 1, (epnum & 1) ? "in" : "out",


	dwc3_ep0_state_string(dwc->ep0state));



switch (event->endpoint_event) {
case DWC3_DEPEVT_XFERCOMPLETE:
dwc3_ep0_xfer_complete(dwc, event);


break;



case DWC3_DEPEVT_XFERNOTREADY:
dwc3_ep0_xfernotready(dwc, event);


break;



case DWC3_DEPEVT_XFERINPROGRESS:
case DWC3_DEPEVT_RXTXFIFOEVT:
case DWC3_DEPEVT_STREAMEVT:
case DWC3_DEPEVT_EPCMDCMPLT:
break;


}

+}
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
new file mode 100644
index 0000000..aba9255
--- /dev/null
+++ b/drivers/usb/dwc3/gadget.c
@@ -0,0 +1,2806 @@
+/**


gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link







Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com







Authors: Felipe Balbi balbi@ti.com,



   Sebastian Andrzej Siewior <bigeasy@linutronix.de>









Back-ported by: Dan Murphy dmurphy@ti.com







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions, and the following disclaimer,



without modification.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




The names of the above-listed copyright holders may not be used





to endorse or promote products derived from this software without



specific prior written permission.







ALTERNATIVELY, this software may be distributed under the terms of the



GNU General Public License ("GPL") version 2, as published by the Free



Software Foundation.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS



IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,



THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR



PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR



CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,



EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,



PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR



PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF



LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING



NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS



SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


*/


+#define __UBOOT__
+#ifndef __UBOOT__
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/list.h>
+#include <linux/dma-mapping.h>



+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>



+#else



+#include <common.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/linux-compat.h>
+#include <usb/lin_gadget_compat.h>



+#endif



+#include "core.h"
+#include "gadget.h"
+#include "io.h"



+/**


dwc3_gadget_set_test_mode - Enables USB2 Test Modes



@dwc: pointer to our context structure



@mode: the mode to set (J, K SE0 NAK, Force Enable)







Caller should take care of locking. This function will



return 0 on success or -EINVAL if wrong Test Selector



is passed


*/

+int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
+{

u32		reg;

reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg &= ~DWC3_DCTL_TSTCTRL_MASK;

switch (mode) {
case TEST_J:
case TEST_K:
case TEST_SE0_NAK:
case TEST_PACKET:
case TEST_FORCE_EN:
reg |= mode << 1;


break;


default:
return -EINVAL;


}

dwc3_writel(dwc->regs, DWC3_DCTL, reg);

return 0;

+}



+/**


dwc3_gadget_set_link_state - Sets USB Link to a particular State



@dwc: pointer to our context structure



@state: the state to put link into







Caller should take care of locking. This function will



return 0 on success or -ETIMEDOUT.


*/

+int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
+{

int		retries = 10000;
u32		reg;

/*
* Wait until device controller is ready. Only applies to 1.94a and


* later RTL.


*/


if (dwc->revision >= DWC3_REVISION_194A) {
while (--retries) {


	reg = dwc3_readl(dwc->regs, DWC3_DSTS);


	if (reg & DWC3_DSTS_DCNRD)


		udelay(5);


	else


		break;


}



if (retries <= 0)


	return -ETIMEDOUT;


}

reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;

/* set requested state */
reg |= DWC3_DCTL_ULSTCHNGREQ(state);
dwc3_writel(dwc->regs, DWC3_DCTL, reg);

/*
* The following code is racy when called from dwc3_gadget_wakeup,


* and is not needed, at least on newer versions


*/


if (dwc->revision >= DWC3_REVISION_194A)
return 0;



/* wait for a change in DSTS */
retries = 10000;
while (--retries) {
reg = dwc3_readl(dwc->regs, DWC3_DSTS);



if (DWC3_DSTS_USBLNKST(reg) == state)


	return 0;



udelay(5);


}

dev_vdbg(dwc->dev, "link state change request timed out\n");

return -ETIMEDOUT;

+}



+/**


dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case



@dwc: pointer to our context structure







This function will a best effort FIFO allocation in order



to improve FIFO usage and throughput, while still allowing



us to enable as many endpoints as possible.







Keep in mind that this operation will be highly dependent



on the configured size for RAM1 - which contains TxFifo -,



the amount of endpoints enabled on coreConsultant tool, and



the width of the Master Bus.







In the ideal world, we would always be able to satisfy the



following equation:







((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \



(3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes







Unfortunately, due to many variables that's not always the case.


*/

+int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
+{

int		last_fifo_depth = 0;
int		ram1_depth;
int		fifo_size;
int		mdwidth;
int		num;

if (!dwc->needs_fifo_resize)
return 0;



ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);

/* MDWIDTH is represented in bits, we need it in bytes */
mdwidth >>= 3;

/*
* FIXME For now we will only allocate 1 wMaxPacketSize space


* for each enabled endpoint, later patches will come to


* improve this algorithm so that we better use the internal


* FIFO space


*/


for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
struct dwc3_ep	*dep = dwc->eps[num];


int		fifo_number = dep->number >> 1;


int		mult = 1;


int		tmp;



if (!(dep->number & 1))


	continue;



if (!(dep->flags & DWC3_EP_ENABLED))


	continue;



if (usb_endpoint_xfer_bulk(dep->endpoint.desc)


		|| usb_endpoint_xfer_isoc(dep->endpoint.desc))


	mult = 3;



/*


 * REVISIT: the following assumes we will always have enough


 * space available on the FIFO RAM for all possible use cases.


 * Make sure that's true somehow and change FIFO allocation


 * accordingly.


 *


 * If we have Bulk or Isochronous endpoints, we want


 * them to be able to be very, very fast. So we're giving


 * those endpoints a fifo_size which is enough for 3 full


 * packets


 */


tmp = mult * (dep->endpoint.maxpacket + mdwidth);


tmp += mdwidth;



fifo_size = DIV_ROUND_UP(tmp, mdwidth);



fifo_size |= (last_fifo_depth << 16);



dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",


		dep->name, last_fifo_depth, fifo_size & 0xffff);



dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),


		fifo_size);



last_fifo_depth += (fifo_size & 0xffff);


}

return 0;

+}



+void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,

int status)



+{

struct dwc3			*dwc = dep->dwc;
int				i;

if (req->queued) {
i = 0;


do {


	dep->busy_slot++;


	/*


	 * Skip LINK TRB. We can't use req->trb and check for


	 * DWC3_TRBCTL_LINK_TRB because it points the TRB we


	 * just completed (not the LINK TRB).


	 */


	if (((dep->busy_slot & DWC3_TRB_MASK) ==


		DWC3_TRB_NUM- 1) &&


		usb_endpoint_xfer_isoc(dep->endpoint.desc))


		dep->busy_slot++;


} while(++i < req->request.num_mapped_sgs);


req->queued = false;


}
list_del(&req->list);
req->trb = NULL;

if (req->request.status == -EINPROGRESS)
req->request.status = status;



if (dwc->ep0_bounced && dep->number == 0)
dwc->ep0_bounced = false;


else

+#ifndef __UBOOT__

/* FIX THIS DM */
usb_gadget_unmap_request(&dwc->gadget, &req->request,


		req->direction);



+#endif

dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
	req, dep->name, req->request.actual,


	req->request.length, status);



spin_unlock(&dwc->lock);
req->request.complete(&dep->endpoint, &req->request);
spin_lock(&dwc->lock);

+}



+static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
+{

switch (cmd) {
case DWC3_DEPCMD_DEPSTARTCFG:
return "Start New Configuration";


case DWC3_DEPCMD_ENDTRANSFER:
return "End Transfer";


case DWC3_DEPCMD_UPDATETRANSFER:
return "Update Transfer";


case DWC3_DEPCMD_STARTTRANSFER:
return "Start Transfer";


case DWC3_DEPCMD_CLEARSTALL:
return "Clear Stall";


case DWC3_DEPCMD_SETSTALL:
return "Set Stall";


case DWC3_DEPCMD_GETEPSTATE:
return "Get Endpoint State";


case DWC3_DEPCMD_SETTRANSFRESOURCE:
return "Set Endpoint Transfer Resource";


case DWC3_DEPCMD_SETEPCONFIG:
return "Set Endpoint Configuration";


default:
return "UNKNOWN command";


}

+}



+int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
+{

u32		timeout = 500;
u32		reg;

dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);

do {
reg = dwc3_readl(dwc->regs, DWC3_DGCMD);


if (!(reg & DWC3_DGCMD_CMDACT)) {


	dev_vdbg(dwc->dev, "Command Complete --> %d\n",


			DWC3_DGCMD_STATUS(reg));


	return 0;


}



/*


 * We can't sleep here, because it's also called from


 * interrupt context.


 */


timeout--;


if (!timeout)


	return -ETIMEDOUT;


udelay(1);


} while (1);

+}



+int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,

unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)



+{

struct dwc3_ep		*dep = dwc->eps[ep];
u32			timeout = 500;
u32			reg;

dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
	dep->name,


	dwc3_gadget_ep_cmd_string(cmd), params->param0,


	params->param1, params->param2);



dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);

dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
do {
reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));


if (!(reg & DWC3_DEPCMD_CMDACT)) {


	dev_vdbg(dwc->dev, "Command Complete --> %d\n",


			DWC3_DEPCMD_STATUS(reg));


	return 0;


}



/*


 * We can't sleep here, because it is also called from


 * interrupt context.


 */


timeout--;


if (!timeout)


	return -ETIMEDOUT;



udelay(1);


} while (1);

+}



+static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,

struct dwc3_trb *trb)



+{

u32		offset = (char *) trb - (char *) dep->trb_pool;

return dep->trb_pool_dma + offset;

+}



+static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
+{

struct dwc3		*dwc = dep->dwc;

if (dep->trb_pool)
return 0;



if (dep->number == 0 || dep->number == 1)
return 0;



dep->trb_pool = dma_alloc_coherent(dwc->dev,
	sizeof(struct dwc3_trb) * DWC3_TRB_NUM,


	&dep->trb_pool_dma, GFP_KERNEL);


if (!dep->trb_pool) {
dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",


		dep->name);


return -ENOMEM;


}

return 0;

+}



+static void dwc3_free_trb_pool(struct dwc3_ep *dep)
+{

struct dwc3		*dwc = dep->dwc;

dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
	dep->trb_pool, dep->trb_pool_dma);



dep->trb_pool = NULL;
dep->trb_pool_dma = 0;

+}



+static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
+{

struct dwc3_gadget_ep_cmd_params params;
u32			cmd;

memset(&params, 0x00, sizeof(params));

if (dep->number != 1) {
cmd = DWC3_DEPCMD_DEPSTARTCFG;


/* XferRscIdx == 0 for ep0 and 2 for the remaining */


if (dep->number > 1) {


	if (dwc->start_config_issued)


		return 0;


	dwc->start_config_issued = true;


	cmd |= DWC3_DEPCMD_PARAM(2);


}



return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);


}

return 0;

+}



+static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,

const struct usb_endpoint_descriptor *desc,


const struct usb_ss_ep_comp_descriptor *comp_desc,


bool ignore)



+{

struct dwc3_gadget_ep_cmd_params params;

memset(&params, 0x00, sizeof(params));

params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
| DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));



/* Burst size is only needed in SuperSpeed mode */
if (dwc->gadget.speed == USB_SPEED_SUPER) {
u32 burst = dep->endpoint.maxburst - 1;



params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);


}

if (ignore)
params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;



params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
| DWC3_DEPCFG_XFER_NOT_READY_EN;



if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE


	| DWC3_DEPCFG_STREAM_EVENT_EN;


dep->stream_capable = true;


}

if (usb_endpoint_xfer_isoc(desc))
params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;



/*
* We are doing 1:1 mapping for endpoints, meaning


* Physical Endpoints 2 maps to Logical Endpoint 2 and


* so on. We consider the direction bit as part of the physical


* endpoint number. So USB endpoint 0x81 is 0x03.


*/


params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);

/*
* We must use the lower 16 TX FIFOs even though


* HW might have more


*/


if (dep->direction)
params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);



if (desc->bInterval) {
params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);


dep->interval = 1 << (desc->bInterval - 1);


}

return dwc3_send_gadget_ep_cmd(dwc, dep->number,
	DWC3_DEPCMD_SETEPCONFIG, &params);



+}



+static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
+{

struct dwc3_gadget_ep_cmd_params params;

memset(&params, 0x00, sizeof(params));

params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);

return dwc3_send_gadget_ep_cmd(dwc, dep->number,
	DWC3_DEPCMD_SETTRANSFRESOURCE, &params);



+}



+/**


__dwc3_gadget_ep_enable - Initializes a HW endpoint



@dep: endpoint to be initialized



@desc: USB Endpoint Descriptor







Caller should take care of locking


*/

+static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,

const struct usb_endpoint_descriptor *desc,


const struct usb_ss_ep_comp_descriptor *comp_desc,


bool ignore)



+{

struct dwc3		*dwc = dep->dwc;
u32			reg;
int			ret = -ENOMEM;

if (!(dep->flags & DWC3_EP_ENABLED)) {
ret = dwc3_gadget_start_config(dwc, dep);


if (ret)


	return ret;


}

ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
if (ret)
return ret;



if (!(dep->flags & DWC3_EP_ENABLED)) {
struct dwc3_trb	*trb_st_hw;


struct dwc3_trb	*trb_link;



ret = dwc3_gadget_set_xfer_resource(dwc, dep);


if (ret)


	return ret;



dep->endpoint.desc = desc;


dep->comp_desc = comp_desc;


dep->type = usb_endpoint_type(desc);


dep->flags |= DWC3_EP_ENABLED;



reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);


reg |= DWC3_DALEPENA_EP(dep->number);


dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);



if (!usb_endpoint_xfer_isoc(desc))


	return 0;



memset(&trb_link, 0, sizeof(trb_link));



/* Link TRB for ISOC. The HWO bit is never reset */


trb_st_hw = &dep->trb_pool[0];



trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];



trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));


trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));


trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;


trb_link->ctrl |= DWC3_TRB_CTRL_HWO;


}

return 0;

+}



+static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
+static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
+{

struct dwc3_request		*req;

if (!list_empty(&dep->req_queued)) {
dwc3_stop_active_transfer(dwc, dep->number);



/* - giveback all requests to gadget driver */


while (!list_empty(&dep->req_queued)) {


	req = next_request(&dep->req_queued);



	dwc3_gadget_giveback(dep, req, -ESHUTDOWN);


}


}

while (!list_empty(&dep->request_list)) {
req = next_request(&dep->request_list);



dwc3_gadget_giveback(dep, req, -ESHUTDOWN);


}

+}



+/**


__dwc3_gadget_ep_disable - Disables a HW endpoint



@dep: the endpoint to disable







This function also removes requests which are currently processed ny the



hardware and those which are not yet scheduled.



Caller should take care of locking.


*/

+static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
+{

struct dwc3		*dwc = dep->dwc;
u32			reg;

dwc3_remove_requests(dwc, dep);

reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
reg &= ~DWC3_DALEPENA_EP(dep->number);
dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);

dep->stream_capable = false;
dep->endpoint.desc = NULL;
dep->comp_desc = NULL;
dep->type = 0;
dep->flags = 0;

return 0;

+}



+/* -------------------------------------------------------------------------- */



+static int dwc3_gadget_ep0_enable(struct usb_ep *ep,

const struct usb_endpoint_descriptor *desc)



+{

return -EINVAL;

+}



+static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
+{

return -EINVAL;

+}



+/* -------------------------------------------------------------------------- */



+static int dwc3_gadget_ep_enable(struct usb_ep *ep,

const struct usb_endpoint_descriptor *desc)



+{

struct dwc3_ep			*dep;
struct dwc3			*dwc;
unsigned long			flags;
int				ret;

if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
pr_debug("dwc3: invalid parameters\n");


return -EINVAL;


}

if (!desc->wMaxPacketSize) {
pr_debug("dwc3: missing wMaxPacketSize\n");


return -EINVAL;


}

dep = to_dwc3_ep(ep);
dwc = dep->dwc;

if (dep->flags & DWC3_EP_ENABLED) {

+#ifndef __UBOOT__

dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",


		dep->name);



+#else

printf("%s is already enabled\n", dep->name);



+#endif

return 0;


}

switch (usb_endpoint_type(desc)) {
case USB_ENDPOINT_XFER_CONTROL:

+#ifndef __UBOOT__

strlcat(dep->name, "-control", sizeof(dep->name));



+#else

strcat(dep->name, "-control");



+#endif

break;


case USB_ENDPOINT_XFER_ISOC:

+#ifndef __UBOOT__

strlcat(dep->name, "-isoc", sizeof(dep->name));



+#else

strcat(dep->name, "-isoc");



+#endif

break;


case USB_ENDPOINT_XFER_BULK:

+#ifndef __UBOOT__

strlcat(dep->name, "-bulk", sizeof(dep->name));



+#else

strcat(dep->name, "-bulk");



+#endif

break;


case USB_ENDPOINT_XFER_INT:

+#ifndef __UBOOT__

strlcat(dep->name, "-int", sizeof(dep->name));



+#else

strcat(dep->name, "-int");



+#endif

break;


default:
dev_err(dwc->dev, "invalid endpoint transfer type\n");


}

dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);

spin_lock_irqsave(&dwc->lock, flags);
ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
spin_unlock_irqrestore(&dwc->lock, flags);

return ret;

+}



+static int dwc3_gadget_ep_disable(struct usb_ep *ep)
+{

struct dwc3_ep			*dep;
struct dwc3			*dwc;
unsigned long			flags;
int				ret;

if (!ep) {
pr_debug("dwc3: invalid parameters\n");


return -EINVAL;


}

dep = to_dwc3_ep(ep);
dwc = dep->dwc;

if (!(dep->flags & DWC3_EP_ENABLED)) {

+#ifndef __UBOOT__

dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",


		dep->name);



+#else

printf("%s is already disabled\n", dep->name);



+#endif

return 0;


}

snprintf(dep->name, sizeof(dep->name), "ep%d%s",
	dep->number >> 1,


	(dep->number & 1) ? "in" : "out");



spin_lock_irqsave(&dwc->lock, flags);
ret = __dwc3_gadget_ep_disable(dep);
spin_unlock_irqrestore(&dwc->lock, flags);

return ret;

+}



+static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,

gfp_t gfp_flags)

+{

struct dwc3_request		*req;
struct dwc3_ep			*dep = to_dwc3_ep(ep);
struct dwc3			*dwc = dep->dwc;

req = kzalloc(sizeof(*req), gfp_flags);
if (!req) {
dev_err(dwc->dev, "not enough memory\n");


return NULL;


}

req->epnum	= dep->number;
req->dep	= dep;

return &req->request;

+}



+static void dwc3_gadget_ep_free_request(struct usb_ep *ep,

struct usb_request *request)



+{

struct dwc3_request		*req = to_dwc3_request(request);

kfree(req);

+}



+/**


dwc3_prepare_one_trb - setup one TRB from one request



@dep: endpoint for which this request is prepared



@req: dwc3_request pointer


*/

+static void dwc3_prepare_one_trb(struct dwc3_ep *dep,

struct dwc3_request *req, dma_addr_t dma,


unsigned length, unsigned last, unsigned chain, unsigned node)



+{

struct dwc3		*dwc = dep->dwc;
struct dwc3_trb		*trb;

dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
	dep->name, req, (unsigned long long) dma,


	length, last ? " last" : "",


	chain ? " chain" : "");



/* Skip the LINK-TRB on ISOC */
if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
	usb_endpoint_xfer_isoc(dep->endpoint.desc))


dep->free_slot++;



trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];

if (!req->trb) {
dwc3_gadget_move_request_queued(req);


req->trb = trb;


req->trb_dma = dwc3_trb_dma_offset(dep, trb);


req->start_slot = dep->free_slot & DWC3_TRB_MASK;


}

dep->free_slot++;

trb->size = DWC3_TRB_SIZE_LENGTH(length);
trb->bpl = lower_32_bits(dma);
trb->bph = upper_32_bits(dma);

switch (usb_endpoint_type(dep->endpoint.desc)) {
case USB_ENDPOINT_XFER_CONTROL:
trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;


break;



case USB_ENDPOINT_XFER_ISOC:
if (!node)


	trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;


else


	trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;



if (!req->request.no_interrupt && !chain)


	trb->ctrl |= DWC3_TRB_CTRL_IOC;


break;



case USB_ENDPOINT_XFER_BULK:
case USB_ENDPOINT_XFER_INT:
trb->ctrl = DWC3_TRBCTL_NORMAL;


break;


default:
/*


 * This is only possible with faulty memory because we


 * checked it already :)


 */


BUG();


}

if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;


trb->ctrl |= DWC3_TRB_CTRL_CSP;


} else if (last) {
trb->ctrl |= DWC3_TRB_CTRL_LST;


}

if (chain)
trb->ctrl |= DWC3_TRB_CTRL_CHN;



if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);



trb->ctrl |= DWC3_TRB_CTRL_HWO;

+}



+/*


dwc3_prepare_trbs - setup TRBs from requests



@dep: endpoint for which requests are being prepared



@starting: true if the endpoint is idle and no requests are queued.







The function goes through the requests list and sets up TRBs for the



transfers. The function returns once there are no more TRBs available or



it runs out of requests.


*/

+static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
+{

struct dwc3_request	*req, *n;
u32			trbs_left;
u32			max;
unsigned int		last_one = 0;

BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);

/* the first request must not be queued */
trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;

/* Can't wrap around on a non-isoc EP since there's no link TRB */
if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);


if (trbs_left > max)


	trbs_left = max;


}

/*
* If busy & slot are equal than it is either full or empty. If we are


* starting to process requests then we are empty. Otherwise we are


* full and don't do anything


*/


if (!trbs_left) {
if (!starting)


	return;


trbs_left = DWC3_TRB_NUM;


/*


 * In case we start from scratch, we queue the ISOC requests


 * starting from slot 1. This is done because we use ring


 * buffer and have no LST bit to stop us. Instead, we place


 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt


 * after the first request so we start at slot 1 and have


 * 7 requests proceed before we hit the first IOC.


 * Other transfer types don't use the ring buffer and are


 * processed from the first TRB until the last one. Since we


 * don't wrap around we have to start at the beginning.


 */


if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {


	dep->busy_slot = 1;


	dep->free_slot = 1;


} else {


	dep->busy_slot = 0;


	dep->free_slot = 0;


}


}

/* The last TRB is a link TRB, not used for xfer */
if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
return;



list_for_each_entry_safe(req, n, &dep->request_list, list) {
unsigned	length;


dma_addr_t	dma;


last_one = false;



if (req->request.num_mapped_sgs > 0) {


	struct usb_request *request = &req->request;


	struct scatterlist *sg = request->sg;


	struct scatterlist *s;


	int		i;



	printf("Fix this\n");



+#ifndef __UBOOT__

/* FIX THIS DM */
	for_each_sg(sg, s, request->num_mapped_sgs, i) {


		unsigned chain = true;



		length = sg_dma_len(s);


		dma = sg_dma_address(s);



		if (i == (request->num_mapped_sgs - 1) ||


				sg_is_last(s)) {


			if (list_is_last(&req->list,


					&dep->request_list))


				last_one = true;


			chain = false;


		}



		trbs_left--;


		if (!trbs_left)


			last_one = true;



		if (last_one)


			chain = false;



		dwc3_prepare_one_trb(dep, req, dma, length,


				last_one, chain, i);



		if (last_one)


			break;


	}



+#endif

} else {


	dma = req->request.dma;


	length = req->request.length;


	trbs_left--;



	if (!trbs_left)


		last_one = 1;



	/* Is this the last request? */


	if (list_is_last(&req->list, &dep->request_list))


		last_one = 1;



	dwc3_prepare_one_trb(dep, req, dma, length,


			last_one, false, 0);



	if (last_one)


		break;


}


}

+}



+static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,

int start_new)



+{

struct dwc3_gadget_ep_cmd_params params;
struct dwc3_request		*req;
struct dwc3			*dwc = dep->dwc;
int				ret;
u32				cmd;

if (start_new && (dep->flags & DWC3_EP_BUSY)) {
dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);


return -EBUSY;


}
dep->flags &= ~DWC3_EP_PENDING_REQUEST;

/*
* If we are getting here after a short-out-packet we don't enqueue any


* new requests as we try to set the IOC bit only on the last request.


*/


if (start_new) {
if (list_empty(&dep->req_queued))


	dwc3_prepare_trbs(dep, start_new);



/* req points to the first request which will be sent */


req = next_request(&dep->req_queued);


} else {
dwc3_prepare_trbs(dep, start_new);



/*


 * req points to the first request where HWO changed from 0 to 1


 */


req = next_request(&dep->req_queued);


}
if (!req) {
dep->flags |= DWC3_EP_PENDING_REQUEST;


return 0;


}

memset(&params, 0, sizeof(params));

if (start_new) {
params.param0 = upper_32_bits(req->trb_dma);


params.param1 = lower_32_bits(req->trb_dma);


cmd = DWC3_DEPCMD_STARTTRANSFER;


} else {
cmd = DWC3_DEPCMD_UPDATETRANSFER;


}

cmd |= DWC3_DEPCMD_PARAM(cmd_param);
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
if (ret < 0) {
dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");



/*


 * FIXME we need to iterate over the list of requests


 * here and stop, unmap, free and del each of the linked


 * requests instead of what we do now.


 */



+#ifndef __UBOOT__

/* FIX THIS DM */
usb_gadget_unmap_request(&dwc->gadget, &req->request,


		req->direction);



+#endif

list_del(&req->list);


return ret;


}

dep->flags |= DWC3_EP_BUSY;

if (start_new) {
dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,


		dep->number);


WARN_ON_ONCE(!dep->resource_index);


}

return 0;

+}



+static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,

struct dwc3_ep *dep, u32 cur_uf)



+{

u32 uf;

if (list_empty(&dep->request_list)) {
dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",


	dep->name);


dep->flags |= DWC3_EP_PENDING_REQUEST;


return;


}

/* 4 micro frames in the future */
uf = cur_uf + dep->interval * 4;

__dwc3_gadget_kick_transfer(dep, uf, 1);

+}



+static void dwc3_gadget_start_isoc(struct dwc3 *dwc,

struct dwc3_ep *dep, const struct dwc3_event_depevt *event)



+{

u32 cur_uf, mask;

mask = ~(dep->interval - 1);
cur_uf = event->parameters & mask;

__dwc3_gadget_start_isoc(dwc, dep, cur_uf);

+}



+static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
+{

struct dwc3		*dwc = dep->dwc;
int			ret;

req->request.actual	= 0;
req->request.status	= -EINPROGRESS;
req->direction		= dep->direction;
req->epnum		= dep->number;

/*
* We only add to our list of requests now and


* start consuming the list once we get XferNotReady


* IRQ.


*


* That way, we avoid doing anything that we don't need


* to do now and defer it until the point we receive a


* particular token from the Host side.


*


* This will also avoid Host cancelling URBs due to too


* many NAKs.


*/



+#ifndef __UBOOT__

/* FIX THIS DM */
ret = usb_gadget_map_request(&dwc->gadget, &req->request,
	dep->direction);


if (ret)
return ret;



+#endif

list_add_tail(&req->list, &dep->request_list);

/*
* There are a few special cases:


*


* 1. XferNotReady with empty list of requests. We need to kick the


*    transfer here in that situation, otherwise we will be NAKing


*    forever. If we get XferNotReady before gadget driver has a


*    chance to queue a request, we will ACK the IRQ but won't be


*    able to receive the data until the next request is queued.


*    The following code is handling exactly that.


*


*/


if (dep->flags & DWC3_EP_PENDING_REQUEST) {
/*


 * If xfernotready is already elapsed and it is a case


 * of isoc transfer, then issue END TRANSFER, so that


 * you can receive xfernotready again and can have


 * notion of current microframe.


 */


if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {


	if (list_empty(&dep->req_queued)) {


		dwc3_stop_active_transfer(dwc, dep->number);


		dep->flags = DWC3_EP_ENABLED;


	}


	return 0;


}



ret = __dwc3_gadget_kick_transfer(dep, 0, true);


if (ret && ret != -EBUSY)


	dev_dbg(dwc->dev, "%s: failed to kick transfers\n",


			dep->name);


return ret;


}

/*
* 2. XferInProgress on Isoc EP with an active transfer. We need to


*    kick the transfer here after queuing a request, otherwise the


*    core may not see the modified TRB(s).


*/


if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
	(dep->flags & DWC3_EP_BUSY) &&


	!(dep->flags & DWC3_EP_MISSED_ISOC)) {


WARN_ON_ONCE(!dep->resource_index);


ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,


		false);


if (ret && ret != -EBUSY)


	dev_dbg(dwc->dev, "%s: failed to kick transfers\n",


			dep->name);


return ret;


}

return 0;

+}



+static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,

gfp_t gfp_flags)

+{

struct dwc3_request		*req = to_dwc3_request(request);
struct dwc3_ep			*dep = to_dwc3_ep(ep);
struct dwc3			*dwc = dep->dwc;

unsigned long			flags;

int				ret;

if (!dep->endpoint.desc) {
dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",


		request, ep->name);


return -ESHUTDOWN;


}

dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
	request, ep->name, request->length);



spin_lock_irqsave(&dwc->lock, flags);
ret = __dwc3_gadget_ep_queue(dep, req);
spin_unlock_irqrestore(&dwc->lock, flags);

return ret;

+}



+static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,

struct usb_request *request)



+{

struct dwc3_request		*req = to_dwc3_request(request);
struct dwc3_request		*r = NULL;

struct dwc3_ep			*dep = to_dwc3_ep(ep);
struct dwc3			*dwc = dep->dwc;

unsigned long			flags;
int				ret = 0;

spin_lock_irqsave(&dwc->lock, flags);
list_for_each_entry(r, &dep->request_list, list) {
if (r == req)


	break;


}

if (r != req) {
list_for_each_entry(r, &dep->req_queued, list) {


	if (r == req)


		break;


}


if (r == req) {


	/* wait until it is processed */


	dwc3_stop_active_transfer(dwc, dep->number);


	goto out1;


}


dev_err(dwc->dev, "request %p was not queued to %s\n",


		request, ep->name);


ret = -EINVAL;


goto out0;


}


+out1:

/* giveback the request */
dwc3_gadget_giveback(dep, req, -ECONNRESET);


+out0:

spin_unlock_irqrestore(&dwc->lock, flags);

return ret;

+}



+int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
+{

struct dwc3_gadget_ep_cmd_params	params;
struct dwc3				*dwc = dep->dwc;
int					ret;

memset(&params, 0x00, sizeof(params));

if (value) {
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,


	DWC3_DEPCMD_SETSTALL, &params);


if (ret)


	dev_err(dwc->dev, "failed to %s STALL on %s\n",


			value ? "set" : "clear",


			dep->name);


else


	dep->flags |= DWC3_EP_STALL;


} else {
if (dep->flags & DWC3_EP_WEDGE)


	return 0;



ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,


	DWC3_DEPCMD_CLEARSTALL, &params);


if (ret)


	dev_err(dwc->dev, "failed to %s STALL on %s\n",


			value ? "set" : "clear",


			dep->name);


else


	dep->flags &= ~DWC3_EP_STALL;


}

return ret;

+}



+static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
+{

struct dwc3_ep			*dep = to_dwc3_ep(ep);
struct dwc3			*dwc = dep->dwc;

unsigned long			flags;

int				ret;

spin_lock_irqsave(&dwc->lock, flags);
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);


ret = -EINVAL;


goto out;


}

ret = __dwc3_gadget_ep_set_halt(dep, value);

+out:

spin_unlock_irqrestore(&dwc->lock, flags);

return ret;

+}



+static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
+{

struct dwc3_ep			*dep = to_dwc3_ep(ep);
struct dwc3			*dwc = dep->dwc;
unsigned long			flags;

spin_lock_irqsave(&dwc->lock, flags);
dep->flags |= DWC3_EP_WEDGE;
spin_unlock_irqrestore(&dwc->lock, flags);

if (dep->number == 0 || dep->number == 1)
return dwc3_gadget_ep0_set_halt(ep, 1);


else
return dwc3_gadget_ep_set_halt(ep, 1);



+}



+/* -------------------------------------------------------------------------- */



+static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {

.bLength	= USB_DT_ENDPOINT_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
.bmAttributes	= USB_ENDPOINT_XFER_CONTROL,

+};



+static const struct usb_ep_ops dwc3_gadget_ep0_ops = {

.enable		= dwc3_gadget_ep0_enable,
.disable	= dwc3_gadget_ep0_disable,
.alloc_request	= dwc3_gadget_ep_alloc_request,
.free_request	= dwc3_gadget_ep_free_request,
.queue		= dwc3_gadget_ep0_queue,
.dequeue	= dwc3_gadget_ep_dequeue,
.set_halt	= dwc3_gadget_ep0_set_halt,
.set_wedge	= dwc3_gadget_ep_set_wedge,

+};



+static const struct usb_ep_ops dwc3_gadget_ep_ops = {

.enable		= dwc3_gadget_ep_enable,
.disable	= dwc3_gadget_ep_disable,
.alloc_request	= dwc3_gadget_ep_alloc_request,
.free_request	= dwc3_gadget_ep_free_request,
.queue		= dwc3_gadget_ep_queue,
.dequeue	= dwc3_gadget_ep_dequeue,
.set_halt	= dwc3_gadget_ep_set_halt,
.set_wedge	= dwc3_gadget_ep_set_wedge,

+};



+/* -------------------------------------------------------------------------- */



+static int dwc3_gadget_get_frame(struct usb_gadget *g)
+{

struct dwc3		*dwc = gadget_to_dwc(g);
u32			reg;

reg = dwc3_readl(dwc->regs, DWC3_DSTS);
return DWC3_DSTS_SOFFN(reg);

+}



+static int dwc3_gadget_wakeup(struct usb_gadget *g)
+{

struct dwc3		*dwc = gadget_to_dwc(g);

unsigned long		timeout;
unsigned long		flags;

u32			reg;

int			ret = 0;

u8			link_state;
u8			speed;

spin_lock_irqsave(&dwc->lock, flags);
/*
* According to the Databook Remote wakeup request should


* be issued only when the device is in early suspend state.


*


* We can check that via USB Link State bits in DSTS register.


*/


reg = dwc3_readl(dwc->regs, DWC3_DSTS);

speed = reg & DWC3_DSTS_CONNECTSPD;
if (speed == DWC3_DSTS_SUPERSPEED) {
dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");


ret = -EINVAL;


goto out;


}

link_state = DWC3_DSTS_USBLNKST(reg);

switch (link_state) {
case DWC3_LINK_STATE_RX_DET:	/* in HS, means Early Suspend */
case DWC3_LINK_STATE_U3:	/* in HS, means SUSPEND */
break;


default:
dev_dbg(dwc->dev, "can't wakeup from link state %d\n",


		link_state);


ret = -EINVAL;


goto out;


}

ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
if (ret < 0) {
dev_err(dwc->dev, "failed to put link in Recovery\n");


goto out;


}

/* Recent versions do this automatically */
if (dwc->revision < DWC3_REVISION_194A) {
/* write zeroes to Link Change Request */


reg = dwc3_readl(dwc->regs, DWC3_DCTL);


reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;


dwc3_writel(dwc->regs, DWC3_DCTL, reg);


}

/* poll until Link State changes to ON */

+#ifndef __UBOOT__

timeout = jiffies + msecs_to_jiffies(100);
while (!time_after(jiffies, timeout)) {

+#else

timeout = 100;
while (timeout != 0) {

+#endif

reg = dwc3_readl(dwc->regs, DWC3_DSTS);



/* in HS, means ON */


if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)


	break;



+#ifdef __UBOOT__

mdelay(1);


timeout--;



+#endif

}

if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
dev_err(dwc->dev, "failed to send remote wakeup\n");


ret = -EINVAL;


}


+out:

spin_unlock_irqrestore(&dwc->lock, flags);

return ret;

+}



+static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,

int is_selfpowered)



+{

struct dwc3		*dwc = gadget_to_dwc(g);
unsigned long		flags;

spin_lock_irqsave(&dwc->lock, flags);
dwc->is_selfpowered = !!is_selfpowered;
spin_unlock_irqrestore(&dwc->lock, flags);

return 0;

+}



+static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
+{

u32			reg;
u32			timeout = 500;

reg = dwc3_readl(dwc->regs, DWC3_DCTL);
if (is_on) {
if (dwc->revision <= DWC3_REVISION_187A) {


	reg &= ~DWC3_DCTL_TRGTULST_MASK;


	reg |= DWC3_DCTL_TRGTULST_RX_DET;


}



if (dwc->revision >= DWC3_REVISION_194A)


	reg &= ~DWC3_DCTL_KEEP_CONNECT;


reg |= DWC3_DCTL_RUN_STOP;


dwc->pullups_connected = true;


} else {
reg &= ~DWC3_DCTL_RUN_STOP;


dwc->pullups_connected = false;


}

dwc3_writel(dwc->regs, DWC3_DCTL, reg);

do {
reg = dwc3_readl(dwc->regs, DWC3_DSTS);


if (is_on) {


	if (!(reg & DWC3_DSTS_DEVCTRLHLT))


		break;


} else {


	if (reg & DWC3_DSTS_DEVCTRLHLT)


		break;


}


timeout--;


if (!timeout)


	return -ETIMEDOUT;


udelay(1);


} while (1);

dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
	dwc->gadget_driver


	? dwc->gadget_driver->function : "no-function",


	is_on ? "connect" : "disconnect");



return 0;

+}



+static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
+{

struct dwc3		*dwc = gadget_to_dwc(g);
unsigned long		flags;
int			ret;

is_on = !!is_on;

spin_lock_irqsave(&dwc->lock, flags);
ret = dwc3_gadget_run_stop(dwc, is_on);
spin_unlock_irqrestore(&dwc->lock, flags);

return ret;

+}



+static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
+{

u32			reg;

/* Enable all but Start and End of Frame IRQs */
reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
	DWC3_DEVTEN_EVNTOVERFLOWEN |


	DWC3_DEVTEN_CMDCMPLTEN |


	DWC3_DEVTEN_ERRTICERREN |


	DWC3_DEVTEN_WKUPEVTEN |


	DWC3_DEVTEN_ULSTCNGEN |


	DWC3_DEVTEN_CONNECTDONEEN |


	DWC3_DEVTEN_USBRSTEN |


	DWC3_DEVTEN_DISCONNEVTEN);



dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);

+}



+static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
+{

/* mask all interrupts */
dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);

+}



+static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
+static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);



+static int dwc3_gadget_start(struct usb_gadget *g,

struct usb_gadget_driver *driver)



+{

struct dwc3		*dwc = gadget_to_dwc(g);
struct dwc3_ep		*dep;
unsigned long		flags;
int			ret = 0;
int			irq;
u32			reg;

spin_lock_irqsave(&dwc->lock, flags);
if (dwc->gadget_driver) {
dev_err(dwc->dev, "%s is already bound to %s\n",


		dwc->gadget.name,


		dwc->gadget_driver->driver.name);


ret = -EBUSY;


goto err0;


}

dwc->gadget_driver	= driver;

reg = dwc3_readl(dwc->regs, DWC3_DCFG);
reg &= ~(DWC3_DCFG_SPEED_MASK);

/**
* WORKAROUND: DWC3 revision < 2.20a have an issue


* which would cause metastability state on Run/Stop


* bit if we try to force the IP to USB2-only mode.


*


* Because of that, we cannot configure the IP to any


* speed other than the SuperSpeed


*


* Refers to:


*


* STAR#9000525659: Clock Domain Crossing on DCTL in


* USB 2.0 Mode


*/


if (dwc->revision < DWC3_REVISION_220A)
reg |= DWC3_DCFG_SUPERSPEED;


else
reg |= dwc->maximum_speed;


dwc3_writel(dwc->regs, DWC3_DCFG, reg);

dwc->start_config_issued = false;

/* Start with SuperSpeed Default */
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);

dep = dwc->eps[0];
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
if (ret) {
dev_err(dwc->dev, "failed to enable %s\n", dep->name);


goto err0;


}

dep = dwc->eps[1];
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
if (ret) {
dev_err(dwc->dev, "failed to enable %s\n", dep->name);


goto err1;


}

/* begin to receive SETUP packets */
dwc->ep0state = EP0_SETUP_PHASE;
dwc3_ep0_out_start(dwc);

+#ifndef __UBOOT__

irq = platform_get_irq(to_platform_device(dwc->dev), 0);
ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
	IRQF_SHARED | IRQF_ONESHOT, "dwc3", dwc);


if (ret) {
dev_err(dwc->dev, "failed to request irq #%d --> %d\n",


		irq, ret);


goto err1;


}

+#endif /* __UBOOT__ */

dwc3_gadget_enable_irq(dwc);
spin_unlock_irqrestore(&dwc->lock, flags);

return 0;


+err1:

__dwc3_gadget_ep_disable(dwc->eps[0]);


+err0:

spin_unlock_irqrestore(&dwc->lock, flags);

return ret;

+}



+static int dwc3_gadget_stop(struct usb_gadget *g,

struct usb_gadget_driver *driver)



+{

struct dwc3		*dwc = gadget_to_dwc(g);
unsigned long		flags;
int			irq;

spin_lock_irqsave(&dwc->lock, flags);
dwc3_gadget_disable_irq(dwc);

+#ifndef __UBOOT__

irq = platform_get_irq(to_platform_device(dwc->dev), 0);
free_irq(irq, dwc);

+#endif

__dwc3_gadget_ep_disable(dwc->eps[0]);
__dwc3_gadget_ep_disable(dwc->eps[1]);

dwc->gadget_driver	= NULL;

spin_unlock_irqrestore(&dwc->lock, flags);

return 0;

+}



+static const struct usb_gadget_ops dwc3_gadget_ops = {

.get_frame		= dwc3_gadget_get_frame,
.wakeup			= dwc3_gadget_wakeup,
.set_selfpowered	= dwc3_gadget_set_selfpowered,
.pullup			= dwc3_gadget_pullup,
.udc_start		= dwc3_gadget_start,
.udc_stop		= dwc3_gadget_stop,

+};



+/* -------------------------------------------------------------------------- */



+static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,

u8 num, u32 direction)



+{

struct dwc3_ep			*dep;
u8				i;

for (i = 0; i < num; i++) {
u8 epnum = (i << 1) | (!!direction);



dep = kzalloc(sizeof(*dep), GFP_KERNEL);


if (!dep) {


	dev_err(dwc->dev, "can't allocate endpoint %d\n",


			epnum);


	return -ENOMEM;


}



dep->dwc = dwc;


dep->number = epnum;


dwc->eps[epnum] = dep;



snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,


		(epnum & 1) ? "in" : "out");



dep->endpoint.name = dep->name;


dep->direction = (epnum & 1);



if (epnum == 0 || epnum == 1) {


	dep->endpoint.maxpacket = 512;


	dep->endpoint.maxburst = 1;


	dep->endpoint.ops = &dwc3_gadget_ep0_ops;


	if (!epnum)


		dwc->gadget.ep0 = &dep->endpoint;


} else {


	int		ret;



	dep->endpoint.maxpacket = 1024;


	dep->endpoint.max_streams = 15;


	dep->endpoint.ops = &dwc3_gadget_ep_ops;


	list_add_tail(&dep->endpoint.ep_list,


			&dwc->gadget.ep_list);



	ret = dwc3_alloc_trb_pool(dep);


	if (ret)


		return ret;


}



INIT_LIST_HEAD(&dep->request_list);


INIT_LIST_HEAD(&dep->req_queued);


}

return 0;

+}



+static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
+{

int				ret;

INIT_LIST_HEAD(&dwc->gadget.ep_list);

ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
if (ret < 0) {
dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");


return ret;


}

ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
if (ret < 0) {
dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");


return ret;


}

return 0;

+}



+static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
+{

struct dwc3_ep			*dep;
u8				epnum;

for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
dep = dwc->eps[epnum];


if (!dep)


	continue;



dwc3_free_trb_pool(dep);



if (epnum != 0 && epnum != 1)


	list_del(&dep->endpoint.ep_list);



kfree(dep);


}

+}



+/* -------------------------------------------------------------------------- */



+static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,

struct dwc3_request *req, struct dwc3_trb *trb,


const struct dwc3_event_depevt *event, int status)



+{

unsigned int		count;
unsigned int		s_pkt = 0;
unsigned int		trb_status;

if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
/*


 * We continue despite the error. There is not much we


 * can do. If we don't clean it up we loop forever. If


 * we skip the TRB then it gets overwritten after a


 * while since we use them in a ring buffer. A BUG()


 * would help. Lets hope that if this occurs, someone


 * fixes the root cause instead of looking away :)


 */


dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",


		dep->name, trb);


count = trb->size & DWC3_TRB_SIZE_MASK;

if (dep->direction) {
if (count) {


	trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);


	if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {


		dev_dbg(dwc->dev, "incomplete IN transfer %s\n",


				dep->name);


		/*


		 * If missed isoc occurred and there is


		 * no request queued then issue END


		 * TRANSFER, so that core generates


		 * next xfernotready and we will issue


		 * a fresh START TRANSFER.


		 * If there are still queued request


		 * then wait, do not issue either END


		 * or UPDATE TRANSFER, just attach next


		 * request in request_list during


		 * giveback.If any future queued request


		 * is successfully transferred then we


		 * will issue UPDATE TRANSFER for all


		 * request in the request_list.


		 */


		dep->flags |= DWC3_EP_MISSED_ISOC;


	} else {


		dev_err(dwc->dev, "incomplete IN transfer %s\n",


				dep->name);


		status = -ECONNRESET;


	}


} else {


	dep->flags &= ~DWC3_EP_MISSED_ISOC;


}


} else {
if (count && (event->status & DEPEVT_STATUS_SHORT))


	s_pkt = 1;


}

/*
* We assume here we will always receive the entire data block


* which we should receive. Meaning, if we program RX to


* receive 4K but we receive only 2K, we assume that's all we


* should receive and we simply bounce the request back to the


* gadget driver for further processing.


*/


req->request.actual += req->request.length - count;
if (s_pkt)
return 1;


if ((event->status & DEPEVT_STATUS_LST) &&
	(trb->ctrl & (DWC3_TRB_CTRL_LST |


		DWC3_TRB_CTRL_HWO)))


return 1;


if ((event->status & DEPEVT_STATUS_IOC) &&
	(trb->ctrl & DWC3_TRB_CTRL_IOC))


return 1;


return 0;

+}



+static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,

const struct dwc3_event_depevt *event, int status)



+{

struct dwc3_request	*req;
struct dwc3_trb		*trb;
unsigned int		slot;
unsigned int		i;
int			ret;

do {
req = next_request(&dep->req_queued);


if (!req) {


	WARN_ON_ONCE(1);


	return 1;


}


i = 0;


do {


	slot = req->start_slot + i;


	if ((slot == DWC3_TRB_NUM - 1) &&


		usb_endpoint_xfer_isoc(dep->endpoint.desc))


		slot++;


	slot %= DWC3_TRB_NUM;


	trb = &dep->trb_pool[slot];



	ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,


			event, status);


	if (ret)


		break;


}while (++i < req->request.num_mapped_sgs);



dwc3_gadget_giveback(dep, req, status);



if (ret)


	break;


} while (1);

if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
	list_empty(&dep->req_queued)) {


if (list_empty(&dep->request_list)) {


	/*


	 * If there is no entry in request list then do


	 * not issue END TRANSFER now. Just set PENDING


	 * flag, so that END TRANSFER is issued when an


	 * entry is added into request list.


	 */


	dep->flags = DWC3_EP_PENDING_REQUEST;


} else {


	dwc3_stop_active_transfer(dwc, dep->number);


	dep->flags = DWC3_EP_ENABLED;


}


return 1;


}

if ((event->status & DEPEVT_STATUS_IOC) &&
	(trb->ctrl & DWC3_TRB_CTRL_IOC))


return 0;


return 1;

+}



+static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,

struct dwc3_ep *dep, const struct dwc3_event_depevt *event,


int start_new)



+{

unsigned		status = 0;
int			clean_busy;

if (event->status & DEPEVT_STATUS_BUSERR)
status = -ECONNRESET;



clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
if (clean_busy)
dep->flags &= ~DWC3_EP_BUSY;



/*
* WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.


* See dwc3_gadget_linksts_change_interrupt() for 1st half.


*/


if (dwc->revision < DWC3_REVISION_183A) {
u32		reg;


int		i;



for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {


	dep = dwc->eps[i];



	if (!(dep->flags & DWC3_EP_ENABLED))


		continue;



	if (!list_empty(&dep->req_queued))


		return;


}



reg = dwc3_readl(dwc->regs, DWC3_DCTL);


reg |= dwc->u1u2;


dwc3_writel(dwc->regs, DWC3_DCTL, reg);



dwc->u1u2 = 0;


}

+}



+static void dwc3_endpoint_interrupt(struct dwc3 *dwc,

const struct dwc3_event_depevt *event)



+{

struct dwc3_ep		*dep;
u8			epnum = event->endpoint_number;

dep = dwc->eps[epnum];

if (!(dep->flags & DWC3_EP_ENABLED))
return;



dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
	dwc3_ep_event_string(event->endpoint_event));



if (epnum == 0 || epnum == 1) {
dwc3_ep0_interrupt(dwc, event);


return;


}

switch (event->endpoint_event) {
case DWC3_DEPEVT_XFERCOMPLETE:
dep->resource_index = 0;



if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {


	dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",


			dep->name);


	return;


}



dwc3_endpoint_transfer_complete(dwc, dep, event, 1);


break;


case DWC3_DEPEVT_XFERINPROGRESS:
if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {


	dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",


			dep->name);


	return;


}



dwc3_endpoint_transfer_complete(dwc, dep, event, 0);


break;


case DWC3_DEPEVT_XFERNOTREADY:
if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {


	dwc3_gadget_start_isoc(dwc, dep, event);


} else {


	int ret;



	dev_vdbg(dwc->dev, "%s: reason %s\n",


			dep->name, event->status &


			DEPEVT_STATUS_TRANSFER_ACTIVE


			? "Transfer Active"


			: "Transfer Not Active");



	ret = __dwc3_gadget_kick_transfer(dep, 0, 1);


	if (!ret || ret == -EBUSY)


		return;



	dev_dbg(dwc->dev, "%s: failed to kick transfers\n",


			dep->name);


}



break;


case DWC3_DEPEVT_STREAMEVT:
if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {


	dev_err(dwc->dev, "Stream event for non-Bulk %s\n",


			dep->name);


	return;


}



switch (event->status) {


case DEPEVT_STREAMEVT_FOUND:


	dev_vdbg(dwc->dev, "Stream %d found and started\n",


			event->parameters);



	break;


case DEPEVT_STREAMEVT_NOTFOUND:


	/* FALLTHROUGH */


default:


	dev_dbg(dwc->dev, "Couldn't find suitable stream\n");


}


break;


case DWC3_DEPEVT_RXTXFIFOEVT:
dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);


break;


case DWC3_DEPEVT_EPCMDCMPLT:
dev_vdbg(dwc->dev, "Endpoint Command Complete\n");


break;


}

+}



+static void dwc3_disconnect_gadget(struct dwc3 *dwc)
+{

if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
spin_unlock(&dwc->lock);


dwc->gadget_driver->disconnect(&dwc->gadget);


spin_lock(&dwc->lock);


}

+}



+static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
+{

struct dwc3_ep *dep;
struct dwc3_gadget_ep_cmd_params params;
u32 cmd;
int ret;

dep = dwc->eps[epnum];

if (!dep->resource_index)
return;



/*
* NOTICE: We are violating what the Databook says about the


* EndTransfer command. Ideally we would _always_ wait for the


* EndTransfer Command Completion IRQ, but that's causing too


* much trouble synchronizing between us and gadget driver.


*


* We have discussed this with the IP Provider and it was


* suggested to giveback all requests here, but give HW some


* extra time to synchronize with the interconnect. We're using


* an arbitraty 100us delay for that.


*


* Note also that a similar handling was tested by Synopsys


* (thanks a lot Paul) and nothing bad has come out of it.


* In short, what we're doing is:


*


* - Issue EndTransfer WITH CMDIOC bit set


* - Wait 100us


*/



cmd = DWC3_DEPCMD_ENDTRANSFER;
cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
memset(&params, 0, sizeof(params));
ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
WARN_ON_ONCE(ret);
dep->resource_index = 0;
dep->flags &= ~DWC3_EP_BUSY;
udelay(100);

+}



+static void dwc3_stop_active_transfers(struct dwc3 *dwc)
+{

u32 epnum;

for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
struct dwc3_ep *dep;



dep = dwc->eps[epnum];


if (!dep)


	continue;



if (!(dep->flags & DWC3_EP_ENABLED))


	continue;



dwc3_remove_requests(dwc, dep);


}

+}



+static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
+{

u32 epnum;

for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
struct dwc3_ep *dep;


struct dwc3_gadget_ep_cmd_params params;


int ret;



dep = dwc->eps[epnum];


if (!dep)


	continue;



if (!(dep->flags & DWC3_EP_STALL))


	continue;



dep->flags &= ~DWC3_EP_STALL;



memset(&params, 0, sizeof(params));


ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,


		DWC3_DEPCMD_CLEARSTALL, &params);


WARN_ON_ONCE(ret);


}

+}



+static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
+{

int			reg;

dev_vdbg(dwc->dev, "%s\n", __func__);

reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg &= ~DWC3_DCTL_INITU1ENA;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);

reg &= ~DWC3_DCTL_INITU2ENA;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);

dwc3_disconnect_gadget(dwc);
dwc->start_config_issued = false;

dwc->gadget.speed = USB_SPEED_UNKNOWN;
dwc->setup_packet_pending = false;

+}



+static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
+{

u32			reg;

reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));

if (suspend)
reg |= DWC3_GUSB3PIPECTL_SUSPHY;


else
reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;



dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

+}



+static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
+{

u32			reg;

reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));

if (suspend)
reg |= DWC3_GUSB2PHYCFG_SUSPHY;


else
reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;



dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

+}



+static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
+{

u32			reg;

dev_vdbg(dwc->dev, "%s\n", __func__);

/*
* WORKAROUND: DWC3 revisions <1.88a have an issue which


* would cause a missing Disconnect Event if there's a


* pending Setup Packet in the FIFO.


*


* There's no suggested workaround on the official Bug


* report, which states that "unless the driver/application


* is doing any special handling of a disconnect event,


* there is no functional issue".


*


* Unfortunately, it turns out that we _do_ some special


* handling of a disconnect event, namely complete all


* pending transfers, notify gadget driver of the


* disconnection, and so on.


*


* Our suggested workaround is to follow the Disconnect


* Event steps here, instead, based on a setup_packet_pending


* flag. Such flag gets set whenever we have a XferNotReady


* event on EP0 and gets cleared on XferComplete for the


* same endpoint.


*


* Refers to:


*


* STAR#9000466709: RTL: Device : Disconnect event not


* generated if setup packet pending in FIFO


*/


if (dwc->revision < DWC3_REVISION_188A) {
if (dwc->setup_packet_pending)


	dwc3_gadget_disconnect_interrupt(dwc);


}

/* after reset -> Default State */
usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);

/* Recent versions support automatic phy suspend and don't need this */
if (dwc->revision < DWC3_REVISION_194A) {
/* Resume PHYs */


dwc3_gadget_usb2_phy_suspend(dwc, false);


dwc3_gadget_usb3_phy_suspend(dwc, false);


}

if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
dwc3_disconnect_gadget(dwc);



reg = dwc3_readl(dwc->regs, DWC3_DCTL);
reg &= ~DWC3_DCTL_TSTCTRL_MASK;
dwc3_writel(dwc->regs, DWC3_DCTL, reg);
dwc->test_mode = false;

dwc3_stop_active_transfers(dwc);
dwc3_clear_stall_all_ep(dwc);
dwc->start_config_issued = false;

/* Reset device address to zero */
reg = dwc3_readl(dwc->regs, DWC3_DCFG);
reg &= ~(DWC3_DCFG_DEVADDR_MASK);
dwc3_writel(dwc->regs, DWC3_DCFG, reg);

+}



+static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
+{

u32 reg;
u32 usb30_clock = DWC3_GCTL_CLK_BUS;

/*
* We change the clock only at SS but I dunno why I would want to do


* this. Maybe it becomes part of the power saving plan.


*/



if (speed != DWC3_DSTS_SUPERSPEED)
return;



/*
* RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed


* each time on Connect Done.


*/


if (!usb30_clock)
return;



reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
dwc3_writel(dwc->regs, DWC3_GCTL, reg);

+}



+static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
+{

switch (speed) {
case USB_SPEED_SUPER:
dwc3_gadget_usb2_phy_suspend(dwc, true);


break;


case USB_SPEED_HIGH:
case USB_SPEED_FULL:
case USB_SPEED_LOW:
dwc3_gadget_usb3_phy_suspend(dwc, true);


break;


}

+}



+static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
+{

struct dwc3_ep		*dep;
int			ret;
u32			reg;
u8			speed;

dev_vdbg(dwc->dev, "%s\n", __func__);

reg = dwc3_readl(dwc->regs, DWC3_DSTS);
speed = reg & DWC3_DSTS_CONNECTSPD;
dwc->speed = speed;

dwc3_update_ram_clk_sel(dwc, speed);

switch (speed) {
case DWC3_DCFG_SUPERSPEED:
/*


 * WORKAROUND: DWC3 revisions <1.90a have an issue which


 * would cause a missing USB3 Reset event.


 *


 * In such situations, we should force a USB3 Reset


 * event by calling our dwc3_gadget_reset_interrupt()


 * routine.


 *


 * Refers to:


 *


 * STAR#9000483510: RTL: SS : USB3 reset event may


 * not be generated always when the link enters poll


 */


if (dwc->revision < DWC3_REVISION_190A)


	dwc3_gadget_reset_interrupt(dwc);



dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);


dwc->gadget.ep0->maxpacket = 512;


dwc->gadget.speed = USB_SPEED_SUPER;


break;


case DWC3_DCFG_HIGHSPEED:
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);


dwc->gadget.ep0->maxpacket = 64;


dwc->gadget.speed = USB_SPEED_HIGH;


break;


case DWC3_DCFG_FULLSPEED2:
case DWC3_DCFG_FULLSPEED1:
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);


dwc->gadget.ep0->maxpacket = 64;


dwc->gadget.speed = USB_SPEED_FULL;


break;


case DWC3_DCFG_LOWSPEED:
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);


dwc->gadget.ep0->maxpacket = 8;


dwc->gadget.speed = USB_SPEED_LOW;


break;


}

/* Enable USB2 LPM Capability */

if ((dwc->revision > DWC3_REVISION_194A)
	&& (speed != DWC3_DCFG_SUPERSPEED)) {


reg = dwc3_readl(dwc->regs, DWC3_DCFG);


reg |= DWC3_DCFG_LPM_CAP;


dwc3_writel(dwc->regs, DWC3_DCFG, reg);



reg = dwc3_readl(dwc->regs, DWC3_DCTL);


reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);



/*


 * TODO: This should be configurable. For now using


 * maximum allowed HIRD threshold value of 0b1100


 */


reg |= DWC3_DCTL_HIRD_THRES(12);



dwc3_writel(dwc->regs, DWC3_DCTL, reg);


}

/* Recent versions support automatic phy suspend and don't need this */
if (dwc->revision < DWC3_REVISION_194A) {
/* Suspend unneeded PHY */


dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);


}

dep = dwc->eps[0];
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
if (ret) {
dev_err(dwc->dev, "failed to enable %s\n", dep->name);


return;


}

dep = dwc->eps[1];
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
if (ret) {
dev_err(dwc->dev, "failed to enable %s\n", dep->name);


return;


}

/*
* Configure PHY via GUSB3PIPECTLn if required.


*


* Update GTXFIFOSIZn


*


* In both cases reset values should be sufficient.


*/



+}



+static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
+{

dev_vdbg(dwc->dev, "%s\n", __func__);

/*
* TODO take core out of low power mode when that's


* implemented.


*/



dwc->gadget_driver->resume(&dwc->gadget);

+}



+static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,

unsigned int evtinfo)



+{

enum dwc3_link_state	next = evtinfo & DWC3_LINK_STATE_MASK;
unsigned int		pwropt;

/*
* WORKAROUND: DWC3 < 2.50a have an issue when configured without


* Hibernation mode enabled which would show up when device detects


* host-initiated U3 exit.


*


* In that case, device will generate a Link State Change Interrupt


* from U3 to RESUME which is only necessary if Hibernation is


* configured in.


*


* There are no functional changes due to such spurious event and we


* just need to ignore it.


*


* Refers to:


*


* STAR#9000570034 RTL: SS Resume event generated in non-Hibernation


* operational mode


*/


pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
if ((dwc->revision < DWC3_REVISION_250A) &&
	(pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {


if ((dwc->link_state == DWC3_LINK_STATE_U3) &&


		(next == DWC3_LINK_STATE_RESUME)) {


	dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");


	return;


}


}

/*
* WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending


* on the link partner, the USB session might do multiple entry/exit


* of low power states before a transfer takes place.


*


* Due to this problem, we might experience lower throughput. The


* suggested workaround is to disable DCTL[12:9] bits if we're


* transitioning from U1/U2 to U0 and enable those bits again


* after a transfer completes and there are no pending transfers


* on any of the enabled endpoints.


*


* This is the first half of that workaround.


*


* Refers to:


*


* STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us


* core send LGO_Ux entering U0


*/


if (dwc->revision < DWC3_REVISION_183A) {
if (next == DWC3_LINK_STATE_U0) {


	u32	u1u2;


	u32	reg;



	switch (dwc->link_state) {


	case DWC3_LINK_STATE_U1:


	case DWC3_LINK_STATE_U2:


		reg = dwc3_readl(dwc->regs, DWC3_DCTL);


		u1u2 = reg & (DWC3_DCTL_INITU2ENA


				| DWC3_DCTL_ACCEPTU2ENA


				| DWC3_DCTL_INITU1ENA


				| DWC3_DCTL_ACCEPTU1ENA);



		if (!dwc->u1u2)


			dwc->u1u2 = reg & u1u2;



		reg &= ~u1u2;



		dwc3_writel(dwc->regs, DWC3_DCTL, reg);


		break;


	default:


		/* do nothing */


		break;


	}


}


}

dwc->link_state = next;

dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);

+}



+static void dwc3_gadget_interrupt(struct dwc3 *dwc,

const struct dwc3_event_devt *event)



+{

switch (event->type) {
case DWC3_DEVICE_EVENT_DISCONNECT:
dwc3_gadget_disconnect_interrupt(dwc);


break;


case DWC3_DEVICE_EVENT_RESET:
dwc3_gadget_reset_interrupt(dwc);


break;


case DWC3_DEVICE_EVENT_CONNECT_DONE:
dwc3_gadget_conndone_interrupt(dwc);


break;


case DWC3_DEVICE_EVENT_WAKEUP:
dwc3_gadget_wakeup_interrupt(dwc);


break;


case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);


break;


case DWC3_DEVICE_EVENT_EOPF:
dev_vdbg(dwc->dev, "End of Periodic Frame\n");


break;


case DWC3_DEVICE_EVENT_SOF:
dev_vdbg(dwc->dev, "Start of Periodic Frame\n");


break;


case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
dev_vdbg(dwc->dev, "Erratic Error\n");


break;


case DWC3_DEVICE_EVENT_CMD_CMPL:
dev_vdbg(dwc->dev, "Command Complete\n");


break;


case DWC3_DEVICE_EVENT_OVERFLOW:
dev_vdbg(dwc->dev, "Overflow\n");


break;


default:
dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);


}

+}



+static void dwc3_process_event_entry(struct dwc3 *dwc,

const union dwc3_event *event)



+{

/* Endpoint IRQ, handle it and return early */
if (event->type.is_devspec == 0) {
/* depevt */


return dwc3_endpoint_interrupt(dwc, &event->depevt);


}

switch (event->type.type) {
case DWC3_EVENT_TYPE_DEV:
dwc3_gadget_interrupt(dwc, &event->devt);


break;


/* REVISIT what to do with Carkit and I2C events ? */
default:
dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);


}

+}



+static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
+{

struct dwc3 *dwc = _dwc;
unsigned long flags;
irqreturn_t ret = IRQ_NONE;
int i;

spin_lock_irqsave(&dwc->lock, flags);

for (i = 0; i < dwc->num_event_buffers; i++) {
struct dwc3_event_buffer *evt;


int			left;



evt = dwc->ev_buffs[i];


left = evt->count;



if (!(evt->flags & DWC3_EVENT_PENDING))


	continue;



while (left > 0) {


	union dwc3_event event;



	event.raw = *(u32 *) (evt->buf + evt->lpos);



	dwc3_process_event_entry(dwc, &event);



	/*


	 * FIXME we wrap around correctly to the next entry as


	 * almost all entries are 4 bytes in size. There is one


	 * entry which has 12 bytes which is a regular entry


	 * followed by 8 bytes data. ATM I don't know how


	 * things are organized if we get next to the a


	 * boundary so I worry about that once we try to handle


	 * that.


	 */


	evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;


	left -= 4;



	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(i), 4);


}



evt->count = 0;


evt->flags &= ~DWC3_EVENT_PENDING;


ret = IRQ_HANDLED;


}

spin_unlock_irqrestore(&dwc->lock, flags);

return ret;

+}



+static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
+{

struct dwc3_event_buffer *evt;
u32 count;

evt = dwc->ev_buffs[buf];

count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
count &= DWC3_GEVNTCOUNT_MASK;
if (!count)
return IRQ_NONE;



evt->count = count;
evt->flags |= DWC3_EVENT_PENDING;

return IRQ_WAKE_THREAD;

+}



+static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
+{

struct dwc3			*dwc = _dwc;
int				i;
irqreturn_t			ret = IRQ_NONE;

spin_lock(&dwc->lock);

for (i = 0; i < dwc->num_event_buffers; i++) {
irqreturn_t status;



status = dwc3_process_event_buf(dwc, i);


if (status == IRQ_WAKE_THREAD)


	ret = status;


}

spin_unlock(&dwc->lock);

return ret;

+}



+/**


dwc3_gadget_init - Initializes gadget related registers



@dwc: pointer to our controller context structure







Returns 0 on success otherwise negative errno.


*/

+int dwc3_gadget_init(struct dwc3 *dwc)
+{

u32					reg;
int					ret;

dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
	&dwc->ctrl_req_addr, GFP_KERNEL);


if (!dwc->ctrl_req) {
dev_err(dwc->dev, "failed to allocate ctrl request\n");


ret = -ENOMEM;


goto err0;


}

dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
	&dwc->ep0_trb_addr, GFP_KERNEL);


if (!dwc->ep0_trb) {
dev_err(dwc->dev, "failed to allocate ep0 trb\n");


ret = -ENOMEM;


goto err1;


}

dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
if (!dwc->setup_buf) {
dev_err(dwc->dev, "failed to allocate setup buffer\n");


ret = -ENOMEM;


goto err2;


}

dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
	DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,


	GFP_KERNEL);


if (!dwc->ep0_bounce) {
dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");


ret = -ENOMEM;


goto err3;


}

dwc->gadget.ops			= &dwc3_gadget_ops;
dwc->gadget.max_speed		= USB_SPEED_SUPER;
dwc->gadget.speed		= USB_SPEED_UNKNOWN;
dwc->gadget.sg_supported	= true;
dwc->gadget.name		= "dwc3-gadget";

/*
* REVISIT: Here we should clear all pending IRQs to be


* sure we're starting from a well known location.


*/



ret = dwc3_gadget_init_endpoints(dwc);
if (ret)
goto err4;



reg = dwc3_readl(dwc->regs, DWC3_DCFG);
reg |= DWC3_DCFG_LPM_CAP;
dwc3_writel(dwc->regs, DWC3_DCFG, reg);

/* Enable USB2 LPM and automatic phy suspend only on recent versions */
if (dwc->revision >= DWC3_REVISION_194A) {
dwc3_gadget_usb2_phy_suspend(dwc, false);


dwc3_gadget_usb3_phy_suspend(dwc, false);


}

+#ifndef __UBOOT__

ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
if (ret) {
dev_err(dwc->dev, "failed to register udc\n");


goto err5;


}

+#endif

return 0;


+err5:

dwc3_gadget_free_endpoints(dwc);


+err4:

dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
	dwc->ep0_bounce, dwc->ep0_bounce_addr);




+err3:

kfree(dwc->setup_buf);


+err2:

dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
	dwc->ep0_trb, dwc->ep0_trb_addr);




+err1:

dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
	dwc->ctrl_req, dwc->ctrl_req_addr);




+err0:

return ret;

+}



+/* -------------------------------------------------------------------------- */



+void dwc3_gadget_exit(struct dwc3 *dwc)
+{

usb_del_gadget_udc(&dwc->gadget);

dwc3_gadget_free_endpoints(dwc);

dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
	dwc->ep0_bounce, dwc->ep0_bounce_addr);



kfree(dwc->setup_buf);

dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
	dwc->ep0_trb, dwc->ep0_trb_addr);



dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
	dwc->ctrl_req, dwc->ctrl_req_addr);



+}



+int dwc3_gadget_prepare(struct dwc3 *dwc)
+{

if (dwc->pullups_connected)
dwc3_gadget_disable_irq(dwc);



return 0;

+}



+void dwc3_gadget_complete(struct dwc3 *dwc)
+{

if (dwc->pullups_connected) {
dwc3_gadget_enable_irq(dwc);


dwc3_gadget_run_stop(dwc, true);


}

+}



+int dwc3_gadget_suspend(struct dwc3 *dwc)
+{

__dwc3_gadget_ep_disable(dwc->eps[0]);
__dwc3_gadget_ep_disable(dwc->eps[1]);

dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);

return 0;

+}



+int dwc3_gadget_resume(struct dwc3 *dwc)
+{

struct dwc3_ep		*dep;
int			ret;

/* Start with SuperSpeed Default */
dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);

dep = dwc->eps[0];
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
if (ret)
goto err0;



dep = dwc->eps[1];
ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
if (ret)
goto err1;



/* begin to receive SETUP packets */
dwc->ep0state = EP0_SETUP_PHASE;
dwc3_ep0_out_start(dwc);

dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);

return 0;


+err1:

__dwc3_gadget_ep_disable(dwc->eps[0]);


+err0:

return ret;

+}
diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h
new file mode 100644
index 0000000..23c57fe
--- /dev/null
+++ b/drivers/usb/dwc3/gadget.h
@@ -0,0 +1,196 @@
+/**


gadget.h - DesignWare USB3 DRD Gadget Header







Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com







Authors: Felipe Balbi balbi@ti.com,



   Sebastian Andrzej Siewior <bigeasy@linutronix.de>









Back-ported by: Dan Murphy dmurphy@ti.com







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions, and the following disclaimer,



without modification.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




The names of the above-listed copyright holders may not be used





to endorse or promote products derived from this software without



specific prior written permission.







ALTERNATIVELY, this software may be distributed under the terms of the



GNU General Public License ("GPL") version 2, as published by the Free



Software Foundation.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS



IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,



THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR



PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR



CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,



EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,



PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR



PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF



LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING



NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS



SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


*/


+#ifndef __DRIVERS_USB_DWC3_GADGET_H
+#define __DRIVERS_USB_DWC3_GADGET_H



+#include <linux/list.h>
+#include <linux/usb/gadget.h>
+#include "io.h"



+struct dwc3;
+#define to_dwc3_ep(ep)		(container_of(ep, struct dwc3_ep, endpoint))
+#define gadget_to_dwc(g)	(container_of(g, struct dwc3, gadget))



+/* DEPCFG parameter 1 */
+#define DWC3_DEPCFG_INT_NUM(n)		((n) << 0)
+#define DWC3_DEPCFG_XFER_COMPLETE_EN	(1 << 8)
+#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN	(1 << 9)
+#define DWC3_DEPCFG_XFER_NOT_READY_EN	(1 << 10)
+#define DWC3_DEPCFG_FIFO_ERROR_EN	(1 << 11)
+#define DWC3_DEPCFG_STREAM_EVENT_EN	(1 << 13)
+#define DWC3_DEPCFG_BINTERVAL_M1(n)	((n) << 16)
+#define DWC3_DEPCFG_STREAM_CAPABLE	(1 << 24)
+#define DWC3_DEPCFG_EP_NUMBER(n)	((n) << 25)
+#define DWC3_DEPCFG_BULK_BASED		(1 << 30)
+#define DWC3_DEPCFG_FIFO_BASED		(1 << 31)



+/* DEPCFG parameter 0 */
+#define DWC3_DEPCFG_EP_TYPE(n)		((n) << 1)
+#define DWC3_DEPCFG_MAX_PACKET_SIZE(n)	((n) << 3)
+#define DWC3_DEPCFG_FIFO_NUMBER(n)	((n) << 17)
+#define DWC3_DEPCFG_BURST_SIZE(n)	((n) << 22)
+#define DWC3_DEPCFG_DATA_SEQ_NUM(n)	((n) << 26)
+/* This applies for core versions earlier than 1.94a */
+#define DWC3_DEPCFG_IGN_SEQ_NUM		(1 << 31)
+/* These apply for core versions 1.94a and later */
+#define DWC3_DEPCFG_ACTION_INIT		(0 << 30)
+#define DWC3_DEPCFG_ACTION_RESTORE	(1 << 30)
+#define DWC3_DEPCFG_ACTION_MODIFY	(2 << 30)



+/* DEPXFERCFG parameter 0 */
+#define DWC3_DEPXFERCFG_NUM_XFER_RES(n)	((n) & 0xffff)



+struct dwc3_gadget_ep_cmd_params {

u32	param2;
u32	param1;
u32	param0;

+};



+/* -------------------------------------------------------------------------- */



+#define to_dwc3_request(r)	(container_of(r, struct dwc3_request, request))



+static inline struct dwc3_request *next_request(struct list_head *list)
+{

if (list_empty(list))
return NULL;



return list_first_entry(list, struct dwc3_request, list);

+}



+static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req)
+{

struct dwc3_ep		*dep = req->dep;

req->queued = true;
list_move_tail(&req->list, &dep->req_queued);

+}



+void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,

int status);




+int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
+int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);



+void dwc3_ep0_interrupt(struct dwc3 *dwc,

const struct dwc3_event_depevt *event);



+void dwc3_ep0_out_start(struct dwc3 *dwc);
+int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
+int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,

gfp_t gfp_flags);



+int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value);
+int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,

unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);



+int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param);



+/**


dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW



@dwc: DesignWare USB3 Pointer



@number: DWC endpoint number







Caller should take care of locking


*/

+static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number)
+{

u32			res_id;

res_id = dwc3_readl(dwc->regs, DWC3_DEPCMD(number));

return DWC3_DEPCMD_GET_RSC_IDX(res_id);

+}



+/**


dwc3_gadget_event_string - returns event name



@event: the event code


*/

+static inline const char *dwc3_gadget_event_string(u8 event)
+{

switch (event) {
case DWC3_DEVICE_EVENT_DISCONNECT:
return "Disconnect";


case DWC3_DEVICE_EVENT_RESET:
return "Reset";


case DWC3_DEVICE_EVENT_CONNECT_DONE:
return "Connection Done";


case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
return "Link Status Change";


case DWC3_DEVICE_EVENT_WAKEUP:
return "WakeUp";


case DWC3_DEVICE_EVENT_EOPF:
return "End-Of-Frame";


case DWC3_DEVICE_EVENT_SOF:
return "Start-Of-Frame";


case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
return "Erratic Error";


case DWC3_DEVICE_EVENT_CMD_CMPL:
return "Command Complete";


case DWC3_DEVICE_EVENT_OVERFLOW:
return "Overflow";


}

return "UNKNOWN";

+}



+/**


dwc3_ep_event_string - returns event name



@event: then event code


*/

+static inline const char *dwc3_ep_event_string(u8 event)
+{

switch (event) {
case DWC3_DEPEVT_XFERCOMPLETE:
return "Transfer Complete";


case DWC3_DEPEVT_XFERINPROGRESS:
return "Transfer In-Progress";


case DWC3_DEPEVT_XFERNOTREADY:
return "Transfer Not Ready";


case DWC3_DEPEVT_RXTXFIFOEVT:
return "FIFO";


case DWC3_DEPEVT_STREAMEVT:
return "Stream";


case DWC3_DEPEVT_EPCMDCMPLT:
return "Endpoint Command Complete";


}

return "UNKNOWN";

+}



+#endif /* __DRIVERS_USB_DWC3_GADGET_H */
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
new file mode 100644
index 0000000..0aa3d03
--- /dev/null
+++ b/drivers/usb/dwc3/host.c
@@ -0,0 +1,107 @@
+/**


host.c - DesignWare USB3 DRD Controller Host Glue







Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com







Authors: Felipe Balbi balbi@ti.com,







Back-ported by: Dan Murphy dmurphy@ti.com







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions, and the following disclaimer,



without modification.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




The names of the above-listed copyright holders may not be used





to endorse or promote products derived from this software without



specific prior written permission.







ALTERNATIVELY, this software may be distributed under the terms of the



GNU General Public License ("GPL") version 2, as published by the Free



Software Foundation.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS



IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,



THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR



PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR



CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,



EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,



PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR



PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF



LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING



NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS



SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


*/


+#define __UBOOT__
+#ifndef __UBOOT__
+#include <linux/platform_device.h>
+#endif
+#include "core.h"



+int dwc3_host_init(struct dwc3 *dwc)
+{
+#ifndef __UBOOT__

struct platform_device	*xhci;

+#endif

void *xhci;
int			ret;

+#ifndef __UBOOT__

xhci = platform_device_alloc("xhci-hcd", PLATFORM_DEVID_AUTO);
if (!xhci) {
dev_err(dwc->dev, "couldn't allocate xHCI device\n");


ret = -ENOMEM;


goto err0;


}
dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);

xhci->dev.parent	= dwc->dev;
xhci->dev.dma_mask	= dwc->dev->dma_mask;
xhci->dev.dma_parms	= dwc->dev->dma_parms;


+#else

xhci = kzalloc(sizeof(*dwc), GFP_KERNEL);
if (!xhci) {
dev_err(dev, "not enough memory\n");


return -ENOMEM;


}

+#endif


dwc->xhci = xhci;


+#ifndef __UBOOT__

ret = platform_device_add_resources(xhci, dwc->xhci_resources,
				DWC3_XHCI_RESOURCES_NUM);


if (ret) {
dev_err(dwc->dev, "couldn't add resources to xHCI device\n");


goto err1;


}

ret = platform_device_add(xhci);
if (ret) {
dev_err(dwc->dev, "failed to register xHCI device\n");


goto err1;


}

+#endif

return 0;


+err1:
+#ifndef __UBOOT__

platform_device_put(xhci);

+#endif



+err0:

return ret;

+}



+void dwc3_host_exit(struct dwc3 *dwc)
+{
+#ifndef __UBOOT__

platform_device_unregister(dwc->xhci);

+#endif
+}



diff --git a/drivers/usb/dwc3/io.h b/drivers/usb/dwc3/io.h
new file mode 100644
index 0000000..2b0895a
--- /dev/null
+++ b/drivers/usb/dwc3/io.h
@@ -0,0 +1,81 @@
+/**


io.h - DesignWare USB3 DRD IO Header







Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com







Authors: Felipe Balbi balbi@ti.com,



   Sebastian Andrzej Siewior <bigeasy@linutronix.de>









Back-ported by: Dan Murphy dmurphy@ti.com







Redistribution and use in source and binary forms, with or without



modification, are permitted provided that the following conditions



are met:




Redistributions of source code must retain the above copyright





notice, this list of conditions, and the following disclaimer,



without modification.




Redistributions in binary form must reproduce the above copyright





notice, this list of conditions and the following disclaimer in the



documentation and/or other materials provided with the distribution.




The names of the above-listed copyright holders may not be used





to endorse or promote products derived from this software without



specific prior written permission.







ALTERNATIVELY, this software may be distributed under the terms of the



GNU General Public License ("GPL") version 2, as published by the Free



Software Foundation.







THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS



IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,



THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR



PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR



CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,



EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,



PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR



PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF



LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING



NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS



SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.


*/


+#ifndef __DRIVERS_USB_DWC3_IO_H
+#define __DRIVERS_USB_DWC3_IO_H



+#define __UBOOT__
+#ifndef __UBOOT__
+#include <linux/io.h>
+#else
+#include <asm/io.h>
+#endif



+#include "core.h"



+static inline u32 dwc3_readl(void __iomem *base, u32 offset)
+{

/*
* We requested the mem region starting from the Globals address


* space, see dwc3_probe in core.c.


* However, the offsets are given starting from xHCI address space.


*/



+#ifndef __UBOOT__

return readl(base + (offset - DWC3_GLOBALS_REGS_START));

+#else

return readl(base + offset);

+#endif
+}



+static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
+{

/*
* We requested the mem region starting from the Globals address


* space, see dwc3_probe in core.c.


* However, the offsets are given starting from xHCI address space.


*/



+#ifndef __UBOOT__

writel(value, base + (offset - DWC3_GLOBALS_REGS_START));

+#else

writel(value, (base + offset));

+#endif
+}



+#endif /* __DRIVERS_USB_DWC3_IO_H */

    

Re: [U-Boot] [RFC] [UBOOT] [PATCH v2 3/4] USB: dwc3: Initial back port of dwc3 code

Roger Quadros

Signed-off-by: Dan Murphy dmurphy@ti.com