The IMX6 Datasheets specifies that when the IMX6 LDO is enabled (internal Anatop LDO's for VDD_ARM, VDD_SOC, and VDD_xPU) you need to provide 1350mV on VDD_ARM_IN and VDD_SOC_IN for IMX6Q@1GHz (Automotive) and 1275mV for IMX6DL@800MHz (Industrial). While we are still about 50mV shy on the IMX6Q operating at 1GHz we set it to the max we can and leave it up to the kernel to implement a regulator driver for the LTC3676 and put the LDO's in bypass mode which allows us to drop the voltages by 125mV respectively.
Signed-off-by: Tim Harvey tharvey@gateworks.com --- board/gateworks/gw_ventana/gw_ventana.c | 42 ++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 51925d1..d93dd56 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -1025,22 +1025,32 @@ int power_init_board(void) p = pmic_get("LTC3676_PMIC"); if (p && !pmic_probe(p)) { puts("PMIC: LTC3676\n"); - /* set board-specific scalar to 1225mV for IMX6Q@1GHz */ - if (is_cpu_type(MXC_CPU_MX6Q)) { - /* mask PGOOD during SW1 transition */ - reg = 0x1d | LTC3676_PGOOD_MASK; - pmic_reg_write(p, LTC3676_DVB1B, reg); - /* set SW1 (VDD_SOC) to 1259mV */ - reg = 0x1d; - pmic_reg_write(p, LTC3676_DVB1A, reg); - - /* mask PGOOD during SW3 transition */ - reg = 0x1d | LTC3676_PGOOD_MASK; - pmic_reg_write(p, LTC3676_DVB3B, reg); - /*set SW3 (VDD_ARM) to 1259mV */ - reg = 0x1d; - pmic_reg_write(p, LTC3676_DVB3A, reg); - } + /* + * set board-specific scalar for max CPU frequency + * per CPU based on the LDO enabled Operating Ranges + * defined in the respective IMX6DQ and IMX6SDL + * datasheets. The voltage resulting from the R1/R2 + * feedback inputs on Ventana is 1308mV. Note that this + * is a bit shy of the Vmin of 1350mV in the datasheet + * for LDO enabled mode but is as high as we can go. + * + * We will rely on an OS kernel driver to properly + * regulate these per CPU operating point and use LDO + * bypass mode when using the higher frequency + * operating points to compensate as LDO bypass mode + * allows the rails be 125mV lower. + */ + /* mask PGOOD during SW1 transition */ + pmic_reg_write(p, LTC3676_DVB1B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW1 (VDD_SOC) */ + pmic_reg_write(p, LTC3676_DVB1A, 0x1f); + + /* mask PGOOD during SW3 transition */ + pmic_reg_write(p, LTC3676_DVB3B, + 0x1f | LTC3676_PGOOD_MASK); + /* set SW3 (VDD_ARM) */ + pmic_reg_write(p, LTC3676_DVB3A, 0x1f); } }