[PATCH v2 2/9] riscv: Optimize loading relocation type

't5' already contains relocation type so don't bother reloading it.

Signed-off-by: Bin Meng bmeng@tinylab.org Reviewed-by: Rick Chen rick@andestech.com ---

(no changes since v1)

arch/riscv/cpu/start.S | 1 - 1 file changed, 1 deletion(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 3c8344c345..879bdc1803 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -323,7 +323,6 @@ fix_rela_dyn: add t4, t4, t6

9: - LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */ srli t0, t5, SYM_INDEX /* t0 <--- sym table index */ andi t5, t5, 0xFF /* t5 <--- relocation type */ li t3, RELOC_TYPE