Add compatible strings for the PCIe bridges & EG20T ethernet controller such that the devices are probed during boot, without the user needing to manually cause that to happen by running "pci enum" after boot. This allows for use of the ethernet controller without the manual PCI enumeration step.
We also enable the EG20T GPIO driver to provide the PHY reset GPIO, and support for the Realtek RTL8211E PHY used on the Boston board in order to make ethernet usable.
Signed-off-by: Paul Burton paul.burton@mips.com Cc: Daniel Schwierzeck daniel.schwierzeck@gmail.com Cc: Simon Glass sjg@chromium.org Cc: u-boot@lists.denx.de
---
arch/mips/Kconfig | 1 + arch/mips/dts/img,boston.dts | 8 ++++---- configs/boston32r2_defconfig | 1 + configs/boston32r2el_defconfig | 1 + configs/boston64r2_defconfig | 1 + configs/boston64r2el_defconfig | 1 + include/configs/boston.h | 5 +++++ 7 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d07b92d1b4..a05c65c507 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -92,6 +92,7 @@ config MACH_PIC32 config TARGET_BOSTON bool "Support Boston" select DM + select DM_GPIO select DM_SERIAL select OF_CONTROL select MIPS_CM diff --git a/arch/mips/dts/img,boston.dts b/arch/mips/dts/img,boston.dts index 1d4eeda4e8..78a24dc4a4 100644 --- a/arch/mips/dts/img,boston.dts +++ b/arch/mips/dts/img,boston.dts @@ -130,7 +130,7 @@ };
pci2_root@0,0,0 { - compatible = "pci10ee,7021"; + compatible = "pci10ee,7021", "pci-bridge"; reg = <0x00000000 0 0 0 0>;
#address-cells = <3>; @@ -138,7 +138,7 @@ #interrupt-cells = <1>;
eg20t_bridge@1,0,0 { - compatible = "pci8086,8800"; + compatible = "pci8086,8800", "pci-bridge"; reg = <0x00010000 0 0 0 0>;
#address-cells = <3>; @@ -146,13 +146,13 @@ #interrupt-cells = <1>;
eg20t_mac@2,0,1 { - compatible = "pci8086,8802"; + compatible = "pci8086,8802", "intel,pch-gbe"; reg = <0x00020100 0 0 0 0>; phy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>; };
eg20t_gpio: eg20t_gpio@2,0,2 { - compatible = "pci8086,8803"; + compatible = "pci8086,8803", "intel,eg20t-gpio"; reg = <0x00020200 0 0 0 0>;
gpio-controller; diff --git a/configs/boston32r2_defconfig b/configs/boston32r2_defconfig index 1d21f1643c..3876672ce9 100644 --- a/configs/boston32r2_defconfig +++ b/configs/boston32r2_defconfig @@ -28,6 +28,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y +CONFIG_EG20T_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y diff --git a/configs/boston32r2el_defconfig b/configs/boston32r2el_defconfig index d26adc68f2..715d02a2b9 100644 --- a/configs/boston32r2el_defconfig +++ b/configs/boston32r2el_defconfig @@ -29,6 +29,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y +CONFIG_EG20T_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y diff --git a/configs/boston64r2_defconfig b/configs/boston64r2_defconfig index 1491575af5..ba69f5b45f 100644 --- a/configs/boston64r2_defconfig +++ b/configs/boston64r2_defconfig @@ -29,6 +29,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y +CONFIG_EG20T_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y diff --git a/configs/boston64r2el_defconfig b/configs/boston64r2el_defconfig index 933b5bfc48..465abbd570 100644 --- a/configs/boston64r2el_defconfig +++ b/configs/boston64r2el_defconfig @@ -30,6 +30,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y +CONFIG_EG20T_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y diff --git a/include/configs/boston.h b/include/configs/boston.h index ee4e4a37ea..2ddd1ae6ad 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -69,4 +69,9 @@ (0xb8000000 + (128 << 20) - CONFIG_ENV_SIZE) #endif
+/* + * Ethernet + */ +#define CONFIG_PHY_REALTEK + #endif /* __CONFIGS_BOSTON_H__ */