From: "Mathieu J. Poirier" mathieu.poirier@linaro.org
Enabling timers and clocks in PRCMU and cleaning up mailbox.
Signed-off-by: Mathieu Poirier mathieu.poirier@linaro.org Signed-off-by: John Rigby john.rigby@linaro.org --- Changes for v2: - Cleaned #defines in snowball.h --- arch/arm/cpu/armv7/u8500/Makefile | 2 +- arch/arm/cpu/armv7/u8500/cpu.c | 41 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/u8500/prcmu.c | 30 ++++++++++++++++++++++ arch/arm/include/asm/arch-u8500/prcmu.h | 24 ++++++++++++++---- board/st-ericsson/u8500/u8500_href.c | 2 +- include/configs/snowball.h | 1 + 6 files changed, 93 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile index 77accde..ce8af96 100644 --- a/arch/arm/cpu/armv7/u8500/Makefile +++ b/arch/arm/cpu/armv7/u8500/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
-COBJS = timer.o clock.o prcmu.o +COBJS = timer.o clock.o prcmu.o cpu.o SOBJS = lowlevel.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c new file mode 100644 index 0000000..04f4b19 --- /dev/null +++ b/arch/arm/cpu/armv7/u8500/cpu.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2012 Linaro Limited + * Mathieu Poirier mathieu.poirier@linaro.org + * + * Based on original code from Joakim Axelsson at ST-Ericsson + * (C) Copyright 2010 ST-Ericsson + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/prcmu.h> + +#ifdef CONFIG_ARCH_CPU_INIT +/* + * SOC specific cpu init + */ +int arch_cpu_init(void) +{ + db8500_prcmu_init(); + + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c index 119ead3..6187dcc 100644 --- a/arch/arm/cpu/armv7/u8500/prcmu.c +++ b/arch/arm/cpu/armv7/u8500/prcmu.c @@ -40,6 +40,8 @@ #define PRCM_MBOX_CPU_SET (U8500_PRCMU_BASE + 0x100) #define PRCM_MBOX_CPU_CLR (U8500_PRCMU_BASE + 0x104)
+#define I2C_MBOX_BIT (1 << 5) + static int prcmu_is_ready(void) { int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE; @@ -162,3 +164,31 @@ int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data) return -1; } } + +void u8500_prcmu_enable(u32 *reg) +{ + writel(readl(reg) | (1 << 8), reg); +} + +void db8500_prcmu_init(void) +{ + /* Enable timers */ + writel(1 << 17, PRCM_TCR); + + u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG); + /* PER4CLK does not exist */ + u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG); + /* Only exists in ED but is always ok to write to */ + u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG); + + u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG); + u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG); + + u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG); + + /* Clean up the mailbox interrupts after pre-u-boot code. */ + writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR); +} diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h index 0836983..1fd4d2a 100644 --- a/arch/arm/include/asm/arch-u8500/prcmu.h +++ b/arch/arm/include/asm/arch-u8500/prcmu.h @@ -27,12 +27,23 @@ #define I2C_RD_OK 2 #define I2CWRITE 0
-#define _PRCMU_TCDM_BASE U8500_PRCMU_TCDM_BASE -#define PRCM_XP70_CUR_PWR_STATE (_PRCMU_TCDM_BASE + 0xFFC) /* 4 BYTES */ - -#define PRCM_REQ_MB5 (_PRCMU_TCDM_BASE + 0xE44) /* 4 bytes */ -#define PRCM_ACK_MB5 (_PRCMU_TCDM_BASE + 0xDF4) /* 4 bytes */ +#define PRCMU_BASE U8500_PRCMU_BASE +#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018) +#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C) +#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020) +#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024) +#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C) +#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030) +#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034) +#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038) +#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C) +#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
+#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C) +#define PRCM_TCR (PRCMU_BASE + 0x1C8) +#define PRCM_REQ_MB5 (PRCMU_BASE + 0xE44) +#define PRCM_ACK_MB5 (PRCMU_BASE + 0xDF4) +#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE + 0xFFC) /* Mailbox 5 Requests */ #define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0) #define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1) @@ -52,4 +63,7 @@ extern int prcmu_i2c_read(u8 reg, u16 slave); extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
+void u8500_prcmu_enable(u32 *reg); +void db8500_prcmu_init(void); + #endif /* __MACH_PRCMU_FW_V1_H */ diff --git a/board/st-ericsson/u8500/u8500_href.c b/board/st-ericsson/u8500/u8500_href.c index 6e3fc87..fe72684 100644 --- a/board/st-ericsson/u8500/u8500_href.c +++ b/board/st-ericsson/u8500/u8500_href.c @@ -26,8 +26,8 @@ #include <asm/arch/gpio.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> -#ifdef CONFIG_MMC #include <asm/arch/prcmu.h> +#ifdef CONFIG_MMC #include "../../../drivers/mmc/arm_pl180_mmci.h" #endif
diff --git a/include/configs/snowball.h b/include/configs/snowball.h index 148d6ee..15cb78b 100644 --- a/include/configs/snowball.h +++ b/include/configs/snowball.h @@ -31,6 +31,7 @@ #define CONFIG_SNOWBALL #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF +#define CONFIG_ARCH_CPU_INIT
/* * High Level Configuration Options