Hello Fabio, Tim and all, in the last few weeks I have been debugging some sporadic i.MX6 board boot failures (2020.07 U-Boot, if that matters) and we have some loose indication that they could be RAM related. The effect is that SPL is not able to load U-Boot from the eMMC to DDR and dqs|write_level calibration is failing.
We do write the memory configuration in a pretty simple way, SPL is just iterating thought a list of register address/value, in a very similar way to what was done using the DCD table. Today most of the boards however use a more programmatic approach as introduced by Tim in 2014 [1].
Contrary to that, however, Fabio moved away from this new approach to just raw registers writing for the sabre board [2][3].
I'm a little bit puzzled at the moment, according to the iMX6 reference manual[4], 44.4.2 MMDC initialization, a specific sequence is required to be followed and this is implemented by the `mx6_dram_cfg()`[5] function, but according to what Fabio wrote the raw initialization of registers was just more reliable for mx6sabresd. Fabio, what was the reason?
I would expect that using `mx6_dram_cfg()` is the correct approach and I would expect issue if doing in a different way from what is described in the reference manual. Regarding that I found also this note in the manual interesting:
"A Precharge All command must be issued prior to the MRW command to ensure robust DDR initialization. This command is required to be issued to both chip selects if two chip selects are utilized in the system."
In my tests adding 1ms delay after each MMDC register write seems to have a positive effect and this is going into the direction that using `mx6_dram_cfg()` is the way to go.
Any suggestion? Do I miss something?
Francesco
[1] https://lore.kernel.org/all/1401750807-5975-7-git-send-email-tharvey@gatewor... [2] https://lore.kernel.org/all/1474892066-32005-1-git-send-email-festevam@gmail... [3] https://source.denx.de/u-boot/u-boot/-/commit/3b30eece271cfc4096c2d20048c89e... [4] https://www.nxp.com/webapp/Download?colCode=IMX6DQRM [5] https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-imx/mx6/ddr...