[U-Boot] [PATCH 2/2 v2] armv8:ls1012a: Use common MMDC driver for ls1012a

12 Aug 2016

Let's use common MMDC driver for DDR initialization on
LS1012ARDB, LS1012AQDS, LS1012AFRDM boards.
Signed-off-by: Shengzhou Liu Shengzhou.Liu@nxp.com
---
v2: no change
board/freescale/ls1012afrdm/ls1012afrdm.c | 116 ------------------------------
 board/freescale/ls1012aqds/ls1012aqds.c   | 116 ------------------------------
 board/freescale/ls1012ardb/ls1012ardb.c   | 116 ------------------------------
 include/configs/ls1012afrdm.h             |  22 ++++--
 include/configs/ls1012aqds.h              |  23 +++++-
 include/configs/ls1012ardb.h              |  21 ++++--
 6 files changed, 54 insertions(+), 360 deletions(-)

diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c
index a94a458..0bbb558 100644
--- a/board/freescale/ls1012afrdm/ls1012afrdm.c
+++ b/board/freescale/ls1012afrdm/ls1012afrdm.c
@@ -18,20 +18,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-{
-	int timeout = 1000;
-
-	out_be32(ptr, value);
-
-	while (in_be32(ptr) & bits) {
-		udelay(100);
-		timeout--;
-	}
-	if (timeout <= 0)
-		puts("Error: wait for clear timeout.\n");
-}
-
 int checkboard(void)
 {
    puts("Board: LS1012AFRDM ");
@@ -39,108 +25,6 @@ int checkboard(void)
    return 0;
 }
-void mmdc_init(void)
-{
-	struct mmdc_p_regs *mmdc =
-		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-
-	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
-	/* configure timing parms */
-	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
-	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
-	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
-	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
-
-	/* other parms	*/
-	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
-	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
-	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
-	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
-
-	/* out of reset delays */
-	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
-
-	/* physical parms */
-	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
-	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
-
-       /* Enable MMDC */
-	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
-
-	/* dram init sequence: update MRs */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_3));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
-				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
-
-       /* dram init sequence: ZQCL */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
-	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
-				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
-				FORCE_ZQ_AUTO_CALIBRATION);
-
-       /* Calibrations now: wr lvl */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
-				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_1));
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
-	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
-
-	mdelay(1);
-
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
-	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
-	mdelay(1);
-
-       /* Calibrations now: Read DQS gating calibration */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
-	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
-	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
-	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
-				AUTO_RD_DQS_GATING_CALIBRATION_EN,
-				AUTO_RD_DQS_GATING_CALIBRATION_EN);
-
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_3));
-
-       /* Calibrations now: Read calibration */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
-	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
-	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
-				AUTO_RD_CALIBRATION_EN,
-				AUTO_RD_CALIBRATION_EN);
-
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_3));
-
-       /* PD, SR */
-	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
-	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
-
-       /* refresh scheme */
-	set_wait_for_bits_clear(&mmdc->mdref,
-				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
-				START_REFRESH);
-
-       /* disable CON_REQ */
-	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
-}
-
 int dram_init(void)
 {
    mmdc_init();
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
index 71eea82..392b6c2 100644
--- a/board/freescale/ls1012aqds/ls1012aqds.c
+++ b/board/freescale/ls1012aqds/ls1012aqds.c
@@ -28,20 +28,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-{
-	int timeout = 1000;
-
-	out_be32(ptr, value);
-
-	while (in_be32(ptr) & bits) {
-		udelay(100);
-		timeout--;
-	}
-	if (timeout <= 0)
-		puts("Error: wait for clear timeout.\n");
-}
-
 int checkboard(void)
 {
    char buf[64];
@@ -67,108 +53,6 @@ int checkboard(void)
    return 0;
 }
-void mmdc_init(void)
-{
-	struct mmdc_p_regs *mmdc =
-		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-
-	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
-	/* configure timing parms */
-	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
-	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
-	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
-	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
-
-	/* other parms	*/
-	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
-	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
-	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
-	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
-
-	/* out of reset delays */
-	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
-
-	/* physical parms */
-	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
-	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
-
-       /* Enable MMDC */
-	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
-
-	/* dram init sequence: update MRs */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_3));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
-				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
-
-       /* dram init sequence: ZQCL */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
-	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
-				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
-				FORCE_ZQ_AUTO_CALIBRATION);
-
-       /* Calibrations now: wr lvl */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
-				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_1));
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
-	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
-
-	mdelay(1);
-
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
-	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
-	mdelay(1);
-
-       /* Calibrations now: Read DQS gating calibration */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
-	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
-	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
-	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
-				AUTO_RD_DQS_GATING_CALIBRATION_EN,
-				AUTO_RD_DQS_GATING_CALIBRATION_EN);
-
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_3));
-
-       /* Calibrations now: Read calibration */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
-	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
-	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
-				AUTO_RD_CALIBRATION_EN,
-				AUTO_RD_CALIBRATION_EN);
-
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_3));
-
-       /* PD, SR */
-	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
-	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
-
-       /* refresh scheme */
-	set_wait_for_bits_clear(&mmdc->mdref,
-				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
-				START_REFRESH);
-
-       /* disable CON_REQ */
-	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
-}
-
 int dram_init(void)
 {
    mmdc_init();
diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
index f69768d..80426f6 100644
--- a/board/freescale/ls1012ardb/ls1012ardb.c
+++ b/board/freescale/ls1012ardb/ls1012ardb.c
@@ -22,20 +22,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
-{
-	int timeout = 1000;
-
-	out_be32(ptr, value);
-
-	while (in_be32(ptr) & bits) {
-		udelay(100);
-		timeout--;
-	}
-	if (timeout <= 0)
-		puts("Error: wait for clear timeout.\n");
-}
-
 int checkboard(void)
 {
    u8 in1;
@@ -71,108 +57,6 @@ int checkboard(void)
    return 0;
 }
-void mmdc_init(void)
-{
-	struct mmdc_p_regs *mmdc =
-		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
-
-	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
-	/* configure timing parms */
-	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
-	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
-	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
-	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
-
-	/* other parms	*/
-	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
-	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
-	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
-	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
-
-	/* out of reset delays */
-	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
-
-	/* physical parms */
-	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
-	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
-
-       /* Enable MMDC */
-	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
-
-	/* dram init sequence: update MRs */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_3));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
-				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
-
-       /* dram init sequence: ZQCL */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
-	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
-				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
-				FORCE_ZQ_AUTO_CALIBRATION);
-
-       /* Calibrations now: wr lvl */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
-				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_1));
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
-	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
-
-	mdelay(1);
-
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
-	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
-
-	mdelay(1);
-
-       /* Calibrations now: Read DQS gating calibration */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
-	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
-	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
-	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
-				AUTO_RD_DQS_GATING_CALIBRATION_EN,
-				AUTO_RD_DQS_GATING_CALIBRATION_EN);
-
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_3));
-
-       /* Calibrations now: Read calibration */
-	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
-				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
-	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
-				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
-	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
-	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
-				AUTO_RD_CALIBRATION_EN,
-				AUTO_RD_CALIBRATION_EN);
-
-	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
-				CMD_BANK_ADDR_3));
-
-       /* PD, SR */
-	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
-	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
-
-       /* refresh scheme */
-	set_wait_for_bits_clear(&mmdc->mdref,
-				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
-				START_REFRESH);
-
-       /* disable CON_REQ */
-	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
-}
-
 int dram_init(void)
 {
    mmdc_init();
diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h
index ad81142..22875d9 100644
--- a/include/configs/ls1012afrdm.h
+++ b/include/configs/ls1012afrdm.h
@@ -9,19 +9,33 @@
#include "ls1012a_common.h"
+/* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
 #define CONFIG_NR_DRAM_BANKS		2
 #define CONFIG_SYS_SDRAM_SIZE		0x20000000
-
-#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x04180000
-#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x84180000
-
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
 #define CONFIG_CMD_MEMINFO
 #define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
+/* DDR board-specific timing parameters */
+#define CONFIG_MMDC_MDCTL	0x04180000
+#define CONFIG_MMDC_MDPDC	0x00030035
+#define CONFIG_MMDC_MDOTC	0x12554000
+#define CONFIG_MMDC_MDCFG0	0xbabf7954
+#define CONFIG_MMDC_MDCFG1	0xff328f64
+#define CONFIG_MMDC_MDCFG2	0x01ff00db
+#define CONFIG_MMDC_MDMISC	0x00001680
+#define CONFIG_MMDC_MDREF	0x0f3c8000
+#define CONFIG_MMDC_MDRWD	0x00002000
+#define CONFIG_MMDC_MDOR	0x00bf1023
+#define CONFIG_MMDC_MDASP	0x0000007f
+#define CONFIG_MMDC_MPODTCTRL	0x0000022a
+#define CONFIG_MMDC_MPZQHWCTRL	0xa1390003
+
+
 /*
 * USB
 */
diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
index 6e31ca0..acd607b 100644
--- a/include/configs/ls1012aqds.h
+++ b/include/configs/ls1012aqds.h
@@ -9,14 +9,31 @@
#include "ls1012a_common.h"
-
+/* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
 #define CONFIG_NR_DRAM_BANKS		2
 #define CONFIG_SYS_SDRAM_SIZE		0x40000000
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/* DDR board-specific timing parameters */
+#define CONFIG_MMDC_MDCTL	0x05180000
+#define CONFIG_MMDC_MDPDC	0x00030035
+#define CONFIG_MMDC_MDOTC	0x12554000
+#define CONFIG_MMDC_MDCFG0	0xbabf7954
+#define CONFIG_MMDC_MDCFG1	0xff328f64
+#define CONFIG_MMDC_MDCFG2	0x01ff00db
+#define CONFIG_MMDC_MDMISC	0x00001680
+#define CONFIG_MMDC_MDREF	0x0f3c8000
+#define CONFIG_MMDC_MDRWD	0x00002000
+#define CONFIG_MMDC_MDOR	0x00bf1023
+#define CONFIG_MMDC_MDASP	0x0000007f
+#define CONFIG_MMDC_MPODTCTRL	0x0000022a
+#define CONFIG_MMDC_MPZQHWCTRL	0xa1390003
-#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x05180000
-#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x85180000
/*
  * QIXIS Definitions
diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
index 6046ab7..b2b6280 100644
--- a/include/configs/ls1012ardb.h
+++ b/include/configs/ls1012ardb.h
@@ -9,20 +9,31 @@
#include "ls1012a_common.h"
-
+/* DDR */
 #define CONFIG_DIMM_SLOTS_PER_CTLR	1
 #define CONFIG_CHIP_SELECTS_PER_CTRL	1
 #define CONFIG_NR_DRAM_BANKS		2
 #define CONFIG_SYS_SDRAM_SIZE		0x40000000
-
-#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x05180000
-#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x85180000
-
 #define CONFIG_CMD_MEMINFO
 #define CONFIG_CMD_MEMTEST
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x9fffffff
+/* DDR board-specific timing parameters */
+#define CONFIG_MMDC_MDCTL	0x05180000
+#define CONFIG_MMDC_MDPDC	0x00030035
+#define CONFIG_MMDC_MDOTC	0x12554000
+#define CONFIG_MMDC_MDCFG0	0xbabf7954
+#define CONFIG_MMDC_MDCFG1	0xff328f64
+#define CONFIG_MMDC_MDCFG2	0x01ff00db
+#define CONFIG_MMDC_MDMISC	0x00001680
+#define CONFIG_MMDC_MDREF	0x0f3c8000
+#define CONFIG_MMDC_MDRWD	0x00002000
+#define CONFIG_MMDC_MDOR	0x00bf1023
+#define CONFIG_MMDC_MDASP	0x0000007f
+#define CONFIG_MMDC_MPODTCTRL	0x0000022a
+#define CONFIG_MMDC_MPZQHWCTRL	0xa1390003
+
 /*
 * USB
 */
-- 
2.1.0.27.g96db324


    