* Added PCI and I2C support to CDS flat device tree * Added VIA configuration table * Added support for PCI2 on CDS Patch by Andy Fleming 17-Mar-2006 * Fixed a bug where 8555 PCI code used the old variable and
Signed-off-by: Andy Fleming afleming@freescale.com
---
board/cds/common/ft_board.c | 3 + board/cds/common/via.c | 99 +++++++++++++++++++++++++++ board/cds/common/via.h | 18 +++++ board/cds/mpc8541cds/Makefile | 1 board/cds/mpc8541cds/init.S | 12 ++- board/cds/mpc8541cds/mpc8541cds.c | 32 ++++----- board/cds/mpc8541cds/oftree.dts | 99 +++++++++++++++++++++++++-- board/cds/mpc8548cds/Makefile | 1 board/cds/mpc8548cds/init.S | 12 ++- board/cds/mpc8548cds/mpc8548cds.c | 32 ++++----- board/cds/mpc8548cds/oftree.dts | 131 ++++++++++++++++++++++++++++++++++-- board/cds/mpc8555cds/Makefile | 1 board/cds/mpc8555cds/init.S | 12 ++- board/cds/mpc8555cds/mpc8555cds.c | 39 ++++++----- board/cds/mpc8555cds/oftree.dts | 135 +++++++++++++++++++++++++++++++++++-- include/configs/MPC8541CDS.h | 21 ++---- include/configs/MPC8548CDS.h | 23 ++---- include/configs/MPC8555CDS.h | 23 ++---- create mode 100644 board/cds/common/via.c create mode 100644 board/cds/common/via.h
7fa801f3ea1d0fe73a2aec55965aa0cf58a1997a diff --git a/board/cds/common/ft_board.c b/board/cds/common/ft_board.c index 8c4ef0c..f167e5f 100644 --- a/board/cds/common/ft_board.c +++ b/board/cds/common/ft_board.c @@ -32,6 +32,9 @@ extern void ft_cpu_setup(void *blob, bd_ void ft_board_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif ft_cpu_setup(blob, bd); } #endif diff --git a/board/cds/common/via.c b/board/cds/common/via.c new file mode 100644 index 0000000..68c8d21 --- /dev/null +++ b/board/cds/common/via.c @@ -0,0 +1,99 @@ +/* + * Copyright 2006 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <pci.h> + +/* Config the VIA chip */ +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pci_dev_t bridge; + + /* Enable USB and IDE functions */ + pci_hose_write_config_byte(hose, dev, 0x48, 0x08); + + pciauto_config_device(hose, dev); + + /* + * Force the backplane P2P bridge to have a window + * open from 0x00000000-0x00001fff in PCI I/O space. + * This allows legacy I/O (i8259, etc) on the VIA + * southbridge to be accessed. + */ + bridge = PCI_BDF(0,17,0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); + pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); + pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); + pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); +} + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + /* + * Since the P2P window was forced to cover the fixed + * legacy I/O addresses, it is necessary to manually + * place the base addresses for the IDE and USB functions + * within this window. + */ + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1ff4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1fe8); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_3, 0x1fe4); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fd0); +} + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1fa0); +} + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_4, 0x1f80); +} + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1e00); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_1, 0x1dfc); + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_2, 0x1df8); +} + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) +{ + pciauto_config_device(hose, dev); + + pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1c00); +} + diff --git a/board/cds/common/via.h b/board/cds/common/via.h new file mode 100644 index 0000000..77cfacc --- /dev/null +++ b/board/cds/common/via.h @@ -0,0 +1,18 @@ +#ifndef _MPC85xx_VIA_H +void mpc85xx_config_via(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 1, IDE */ +void mpc85xx_config_via_usbide(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 2, USB ports 0-1 */ +void mpc85xx_config_via_usb(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 3, USB ports 2-3 */ +void mpc85xx_config_via_usb2(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 5, Power Management */ +void mpc85xx_config_via_power(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); + +/* Function 6, AC97 Interface */ +void mpc85xx_config_via_ac97(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab); +#endif /* _MPC85xx_VIA_H */ diff --git a/board/cds/mpc8541cds/Makefile b/board/cds/mpc8541cds/Makefile index 34bc410..7e75357 100644 --- a/board/cds/mpc8541cds/Makefile +++ b/board/cds/mpc8541cds/Makefile @@ -30,6 +30,7 @@ OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ + ../common/via.o \ oftree.o
SOBJS := init.o diff --git a/board/cds/mpc8541cds/init.S b/board/cds/mpc8541cds/init.S index 53dcd0d..978bda5 100644 --- a/board/cds/mpc8541cds/init.S +++ b/board/cds/mpc8541cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c index 6b8aa68..c2b3009 100644 --- a/board/cds/mpc8541cds/mpc8541cds.c +++ b/board/cds/mpc8541cds/mpc8541cds.c @@ -31,6 +31,7 @@
#include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -468,26 +469,25 @@ testdram(void) #endif
#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif
-static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table,}, +#ifdef CONFIG_MPC85XX_PCI2 + {}, #endif };
@@ -497,7 +497,7 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose);
pci_mpc85xx_init(&hose); #endif diff --git a/board/cds/mpc8541cds/oftree.dts b/board/cds/mpc8541cds/oftree.dts index e5d2fd4..bb1096b 100644 --- a/board/cds/mpc8541cds/oftree.dts +++ b/board/cds/mpc8541cds/oftree.dts @@ -54,6 +54,15 @@ reg = <e0000000 00100000>; // CCSRBAR 1M bus-frequency = <0>;
+ i2c@3000 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3000 100>; + interrupts = <6b 0>; + interrupt-parent = <40000>; + dfsrr; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -64,14 +73,14 @@ ethernet-phy@0 { linux,phandle = <2452000>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = <85 0>; reg = <0>; device_type = "ethernet-phy"; }; ethernet-phy@1 { linux,phandle = <2452001>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = <85 0>; reg = <1>; device_type = "ethernet-phy"; }; @@ -85,7 +94,7 @@ compatible = "gianfar"; reg = <24000 1000>; address = [ 00 E0 0C 00 73 00 ]; - interrupts = <d 3 e 3 12 3>; + interrupts = <5d 3 5e 3 62 3>; interrupt-parent = <40000>; phy-handle = <2452000>; }; @@ -98,7 +107,7 @@ compatible = "gianfar"; reg = <25000 1000>; address = [ 00 E0 0C 00 73 01 ]; - interrupts = <13 3 14 3 18 3>; + interrupts = <63 3 64 3 68 3>; interrupt-parent = <40000>; phy-handle = <2452001>; }; @@ -108,7 +117,7 @@ compatible = "ns16550"; reg = <4500 100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <1a 3>; + interrupts = <6a 3>; interrupt-parent = <40000>; };
@@ -117,8 +126,86 @@ compatible = "ns16550"; reg = <4600 100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <1a 3>; + interrupts = <6a 3>; + interrupt-parent = <40000>; + }; + + pci@8000 { + linux,phandle = <8000>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x10 */ + 8000 0 0 1 40000 80 0 + 8000 0 0 2 40000 81 0 + 8000 0 0 3 40000 82 0 + 8000 0 0 4 40000 83 0 + + /* IDSEL 0x11 */ + 8800 0 0 1 40000 80 0 + 8800 0 0 2 40000 81 0 + 8800 0 0 3 40000 82 0 + 8800 0 0 4 40000 83 0 + + /* IDSEL 0x12 */ + 9000 0 0 1 40000 80 0 + 9000 0 0 2 40000 81 0 + 9000 0 0 3 40000 82 0 + 9000 0 0 4 40000 83 0 + + /* IDSEL 0x13 */ + 9800 0 0 1 40000 81 0 + 9800 0 0 2 40000 82 0 + 9800 0 0 3 40000 83 0 + 9800 0 0 4 40000 80 0 + + /* IDSEL 0x14 */ + a000 0 0 1 40000 82 0 + a000 0 0 2 40000 83 0 + a000 0 0 3 40000 80 0 + a000 0 0 4 40000 81 0 + + /* IDSEL 0x15 */ + a800 0 0 1 40000 83 0 + a800 0 0 2 40000 80 0 + a800 0 0 3 40000 81 0 + a800 0 0 4 40000 82 0>; + interrupt-parent = <40000>; + interrupts = <58 0>; + bus-range = <0 0>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <8000 1000>; + compatible = "85xx"; + device_type = "pci"; + }; + + pci@9000 { + linux,phandle = <9000>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x15 */ + a800 0 0 1 40000 8b 0 + a800 0 0 2 40000 8b 0 + a800 0 0 3 40000 8b 0 + a800 0 0 4 40000 8b 0>; interrupt-parent = <40000>; + interrupts = <59 0>; + bus-range = <0 0>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e2100000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <9000 1000>; + compatible = "85xx"; + device_type = "pci"; };
pic@40000 { diff --git a/board/cds/mpc8548cds/Makefile b/board/cds/mpc8548cds/Makefile index caee50b..103e42c 100644 --- a/board/cds/mpc8548cds/Makefile +++ b/board/cds/mpc8548cds/Makefile @@ -30,6 +30,7 @@ OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ + ../common/via.o \ oftree.o
SOBJS := init.o diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S index 53dcd0d..978bda5 100644 --- a/board/cds/mpc8548cds/init.S +++ b/board/cds/mpc8548cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 5bc0890..6eedb4a 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -30,6 +30,7 @@
#include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -293,26 +294,25 @@ testdram(void) #endif
#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it. */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif
-static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table: pci_mpc85xxcds_config_table, +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table,}, +#ifdef CONFIG_MPC85XX_PCI2 + {}, #endif };
@@ -322,7 +322,7 @@ void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose);
pci_mpc85xx_init(&hose); #endif diff --git a/board/cds/mpc8548cds/oftree.dts b/board/cds/mpc8548cds/oftree.dts index 63ae4c9..c0911f2 100644 --- a/board/cds/mpc8548cds/oftree.dts +++ b/board/cds/mpc8548cds/oftree.dts @@ -54,6 +54,15 @@ reg = <e0000000 00100000>; // CCSRBAR 1M bus-frequency = <0>;
+ i2c@3000 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3000 100>; + interrupts = <6b 0>; + interrupt-parent = <40000>; + dfsrr; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -64,14 +73,14 @@ ethernet-phy@0 { linux,phandle = <2452000>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = <85 0>; reg = <0>; device_type = "ethernet-phy"; }; ethernet-phy@1 { linux,phandle = <2452001>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = <85 0>; reg = <1>; device_type = "ethernet-phy"; }; @@ -81,11 +90,11 @@ #address-cells = <1>; #size-cells = <0>; device_type = "network"; - model = "TSEC"; + model = "eTSEC"; compatible = "gianfar"; reg = <24000 1000>; address = [ 00 E0 0C 00 73 00 ]; - interrupts = <d 3 e 3 12 3>; + interrupts = <5d 3 5e 3 62 3>; interrupt-parent = <40000>; phy-handle = <2452000>; }; @@ -94,21 +103,49 @@ #address-cells = <1>; #size-cells = <0>; device_type = "network"; - model = "TSEC"; + model = "eTSEC"; compatible = "gianfar"; reg = <25000 1000>; address = [ 00 E0 0C 00 73 01 ]; - interrupts = <13 3 14 3 18 3>; + interrupts = <63 3 64 3 68 3>; + interrupt-parent = <40000>; + phy-handle = <2452001>; + }; + + ethernet@26000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <26000 1000>; + address = [ 00 E0 0C 00 73 02 ]; + interrupts = <5f 3 60 3 61 3>; interrupt-parent = <40000>; phy-handle = <2452001>; };
+/* eTSEC 4 is currently broken + ethernet@27000 { + #address-cells = <1>; + #size-cells = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <27000 1000>; + address = [ 00 E0 0C 00 73 03 ]; + interrupts = <65 3 66 3 67 3>; + interrupt-parent = <40000>; + phy-handle = <2452001>; + }; + */ + serial@4500 { device_type = "serial"; compatible = "ns16550"; reg = <4500 100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <1a 3>; + interrupts = <6a 3>; interrupt-parent = <40000>; };
@@ -117,8 +154,86 @@ compatible = "ns16550"; reg = <4600 100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <1a 3>; + interrupts = <6a 3>; + interrupt-parent = <40000>; + }; + + pci@8000 { + linux,phandle = <8000>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x10 */ + 8000 0 0 1 40000 80 0 + 8000 0 0 2 40000 81 0 + 8000 0 0 3 40000 82 0 + 8000 0 0 4 40000 83 0 + + /* IDSEL 0x11 */ + 8800 0 0 1 40000 80 0 + 8800 0 0 2 40000 81 0 + 8800 0 0 3 40000 82 0 + 8800 0 0 4 40000 83 0 + + /* IDSEL 0x12 */ + 9000 0 0 1 40000 80 0 + 9000 0 0 2 40000 81 0 + 9000 0 0 3 40000 82 0 + 9000 0 0 4 40000 83 0 + + /* IDSEL 0x13 */ + 9800 0 0 1 40000 81 0 + 9800 0 0 2 40000 82 0 + 9800 0 0 3 40000 83 0 + 9800 0 0 4 40000 80 0 + + /* IDSEL 0x14 */ + a000 0 0 1 40000 82 0 + a000 0 0 2 40000 83 0 + a000 0 0 3 40000 80 0 + a000 0 0 4 40000 81 0 + + /* IDSEL 0x15 */ + a800 0 0 1 40000 83 0 + a800 0 0 2 40000 80 0 + a800 0 0 3 40000 81 0 + a800 0 0 4 40000 82 0>; + interrupt-parent = <40000>; + interrupts = <58 0>; + bus-range = <0 0>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <8000 1000>; + compatible = "85xx"; + device_type = "pci"; + }; + + pci@9000 { + linux,phandle = <9000>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x15 */ + a800 0 0 1 40000 8b 0 + a800 0 0 2 40000 8b 0 + a800 0 0 3 40000 8b 0 + a800 0 0 4 40000 8b 0>; interrupt-parent = <40000>; + interrupts = <59 0>; + bus-range = <0 0>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e2100000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <9000 1000>; + compatible = "85xx"; + device_type = "pci"; };
pic@40000 { diff --git a/board/cds/mpc8555cds/Makefile b/board/cds/mpc8555cds/Makefile index 34bc410..7e75357 100644 --- a/board/cds/mpc8555cds/Makefile +++ b/board/cds/mpc8555cds/Makefile @@ -30,6 +30,7 @@ OBJS := $(BOARD).o \ ../common/cadmus.o \ ../common/eeprom.o \ ../common/ft_board.o \ + ../common/via.o \ oftree.o
SOBJS := init.o diff --git a/board/cds/mpc8555cds/init.S b/board/cds/mpc8555cds/init.S index 53dcd0d..978bda5 100644 --- a/board/cds/mpc8555cds/init.S +++ b/board/cds/mpc8555cds/init.S @@ -210,8 +210,8 @@ tlb1_entry: * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M + * 0xe200_0000 0xe20f_ffff PCI1 IO 1M + * 0xe210_0000 0xe21f_ffff PCI2 IO 1M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M @@ -234,11 +234,11 @@ tlb1_entry: #define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
-#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
-#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) -#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff) +#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ #define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c index 18adf5b..e15bf8f 100644 --- a/board/cds/mpc8555cds/mpc8555cds.c +++ b/board/cds/mpc8555cds/mpc8555cds.c @@ -29,6 +29,7 @@
#include "../common/cadmus.h" #include "../common/eeprom.h" +#include "../common/via.h"
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) extern void ddr_enable_ecc(unsigned int dram_size); @@ -464,38 +465,40 @@ testdram(void) } #endif
-#if defined(CONFIG_PCI) - -/* - * Initialize PCI Devices, report devices found. +#ifdef CONFIG_PCI +/* For some reason the Tundra PCI bridge shows up on itself as a + * different device. Work around that by refusing to configure it */ +void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-#ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxcds_config_table[] = { - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } }, - { } + {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, + {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}}, + {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}}, + {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}}, + {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}}, + {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}}, + {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}} }; -#endif
-static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP + +static struct pci_controller hose[] = { + { config_table: pci_mpc85xxcds_config_table, + }, +#ifdef CONFIG_MPC85XX_PCI2 + { } #endif };
-#endif /* CONFIG_PCI */ +#endif
void pci_init_board(void) { #ifdef CONFIG_PCI - extern void pci_mpc85xx_init(struct pci_controller *hose); + extern void pci_mpc85xx_init(struct pci_controller **hose);
- pci_mpc85xx_init(&hose); + pci_mpc85xx_init(*pci_hose); #endif } diff --git a/board/cds/mpc8555cds/oftree.dts b/board/cds/mpc8555cds/oftree.dts index aa90bce..19491c2 100644 --- a/board/cds/mpc8555cds/oftree.dts +++ b/board/cds/mpc8555cds/oftree.dts @@ -54,6 +54,15 @@ reg = <e0000000 00100000>; // CCSRBAR 1M bus-frequency = <0>;
+ i2c@3000 { + device_type = "i2c"; + compatible = "fsl-i2c"; + reg = <3000 100>; + interrupts = <6b 0>; + interrupt-parent = <40000>; + dfsrr; + }; + mdio@24520 { #address-cells = <1>; #size-cells = <0>; @@ -64,14 +73,14 @@ ethernet-phy@0 { linux,phandle = <2452000>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = <85 0>; reg = <0>; device_type = "ethernet-phy"; }; ethernet-phy@1 { linux,phandle = <2452001>; interrupt-parent = <40000>; - interrupts = <35 0>; + interrupts = <85 0>; reg = <1>; device_type = "ethernet-phy"; }; @@ -85,7 +94,7 @@ compatible = "gianfar"; reg = <24000 1000>; address = [ 00 E0 0C 00 73 00 ]; - interrupts = <d 3 e 3 12 3>; + interrupts = <5d 3 5e 3 62 3>; interrupt-parent = <40000>; phy-handle = <2452000>; }; @@ -98,7 +107,7 @@ compatible = "gianfar"; reg = <25000 1000>; address = [ 00 E0 0C 00 73 01 ]; - interrupts = <13 3 14 3 18 3>; + interrupts = <63 3 64 3 68 3>; interrupt-parent = <40000>; phy-handle = <2452001>; }; @@ -108,7 +117,7 @@ compatible = "ns16550"; reg = <4500 100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <1a 3>; + interrupts = <6a 3>; interrupt-parent = <40000>; };
@@ -117,8 +126,122 @@ compatible = "ns16550"; reg = <4600 100>; // reg base, size clock-frequency = <0>; // should we fill in in uboot? - interrupts = <1a 3>; + interrupts = <6a 3>; + interrupt-parent = <40000>; + }; + + pci@8000 { + linux,phandle = <8000>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x02 */ + 1000 0 0 1 40000 81 0 + 1000 0 0 2 40000 82 0 + 1000 0 0 3 40000 83 0 + 1000 0 0 4 40000 84 0 + + /* IDSEL 0x03 */ + 1800 0 0 1 40000 84 0 + 1800 0 0 2 40000 81 0 + 1800 0 0 3 40000 82 0 + 1800 0 0 4 40000 83 0 + + /* IDSEL 0x04 */ + 2000 0 0 1 40000 83 0 + 2000 0 0 2 40000 84 0 + 2000 0 0 3 40000 81 0 + 2000 0 0 4 40000 82 0 + + /* IDSEL 0x05 */ + 2800 0 0 1 40000 82 0 + 2800 0 0 2 40000 83 0 + 2800 0 0 3 40000 84 0 + 2800 0 0 4 40000 81 0 + + /* IDSEL 0x0c */ + 6000 0 0 1 40000 81 0 + 6000 0 0 2 40000 82 0 + 6000 0 0 3 40000 83 0 + 6000 0 0 4 40000 84 0 + + /* IDSEL 0x0d */ + 6800 0 0 1 40000 84 0 + 6800 0 0 2 40000 81 0 + 6800 0 0 3 40000 82 0 + 6800 0 0 4 40000 83 0 + + /* IDSEL 0x0e */ + 8000 0 0 1 40000 83 0 + 8000 0 0 2 40000 84 0 + 8000 0 0 3 40000 81 0 + 8000 0 0 4 40000 82 0 + + /* IDSEL 0x0f */ + 8800 0 0 1 40000 82 0 + 8800 0 0 2 40000 83 0 + 8800 0 0 3 40000 84 0 + 8800 0 0 4 40000 81 0 + + /* IDSEL 0x12 */ + 9000 0 0 1 40000 81 0 + 9000 0 0 2 40000 82 0 + 9000 0 0 3 40000 83 0 + 9000 0 0 4 40000 84 0 + + /* IDSEL 0x13 */ + 9800 0 0 1 40000 84 0 + 9800 0 0 2 40000 81 0 + 9800 0 0 3 40000 82 0 + 9800 0 0 4 40000 83 0 + + /* IDSEL 0x14 */ + a000 0 0 1 40000 83 0 + a000 0 0 2 40000 84 0 + a000 0 0 3 40000 81 0 + a000 0 0 4 40000 82 0 + + /* IDSEL 0x15 */ + a800 0 0 1 40000 82 0 + a800 0 0 2 40000 83 0 + a800 0 0 3 40000 84 0 + a800 0 0 4 40000 81 0>; + interrupt-parent = <40000>; + interrupts = <58 0>; + bus-range = <0 0>; + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e2000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <8000 1000>; + compatible = "85xx"; + device_type = "pci"; + }; + + pci@9000 { + linux,phandle = <9000>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + + /* IDSEL 0x15 */ + a800 0 0 1 40000 8b 0 + a800 0 0 2 40000 8b 0 + a800 0 0 3 40000 8b 0 + a800 0 0 4 40000 8b 0>; interrupt-parent = <40000>; + interrupts = <89 0>; + bus-range = <0 0>; + ranges = <02000000 0 a0000000 a0000000 0 20000000 + 01000000 0 00000000 e3000000 0 00100000>; + clock-frequency = <3f940aa>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + reg = <9000 1000>; + compatible = "85xx"; + device_type = "pci"; };
pic@40000 { diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 86bcfe3..f73caf0 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void #define OF_CPU "PowerPC,8541@0" #define OF_SOC "soc8541@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8541@e0000000/serial@4600"
/* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,32 +335,27 @@ extern unsigned long get_clock_freq(void #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
#if defined(CONFIG_PCI)
+#define CONFIG_MPC85XX_PCI2 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100 #undef CONFIG_TULIP
-#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b1f8a19..37b518c 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -324,7 +324,7 @@ extern unsigned long get_clock_freq(void #define OF_CPU "PowerPC,8548@0" #define OF_SOC "soc8548@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8548@e0000000/serial@4600"
/* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -341,32 +341,27 @@ extern unsigned long get_clock_freq(void #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_85XX_PCI2
#undef CONFIG_EEPRO100 #undef CONFIG_TULIP
-#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
@@ -386,7 +381,7 @@ extern unsigned long get_clock_freq(void #define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" #define CONFIG_MPC85XX_TSEC3 1 #define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#define CONFIG_MPC85XX_TSEC4 1 +#undef CONFIG_MPC85XX_TSEC4 #define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index b725dac..b94e38a 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -318,7 +318,7 @@ extern unsigned long get_clock_freq(void #define OF_CPU "PowerPC,8555@0" #define OF_SOC "soc8555@e0000000" #define OF_TBCLK (bd->bi_busfreq / 8) -#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4500" +#define OF_STDOUT_PATH "/soc8555@e0000000/serial@4600"
/* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ @@ -335,33 +335,28 @@ extern unsigned long get_clock_freq(void #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
#define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_MPC85XX_PCI2
#undef CONFIG_EEPRO100 #undef CONFIG_TULIP
-#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#endif /* CONFIG_PCI */