at91sam9x5, at91sam9n12, at91sam9g45/m10g45 has plla div2 bits. For other at91 arm926ejs chips, this plla div2 bits (bit-12 in mckr) is reserved and default value after reset is 0. So we can handle all the chip in a same way.
now we can simply remove the chip select macro.
This patch also changes the div2 code to a more readable format.
Signed-off-by: Josh Wu josh.wu@atmel.com --- arch/arm/cpu/arm926ejs/at91/clock.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c index f825388..b6fd2ef 100644 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ b/arch/arm/cpu/arm926ejs/at91/clock.c @@ -155,11 +155,12 @@ int at91_clock_init(unsigned long main_clock) * For now, assume this parentage won't change. */ mckr = readl(&pmc->mckr); -#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ - || defined(CONFIG_AT91SAM9X5) - /* plla divisor by 2 */ - gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); -#endif + + /* plla divisor by 2, Only for AT91SAM9G45, 9M10G45, 9X5, 9N12 */ + /* For other AT91 chip, the bit 12 of MCKR is reserved, default is 0 */ + if (mckr & (1 << 12)) + gd->arch.plla_rate_hz >>= 1; + gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); freq = gd->arch.mck_rate_hz;