On Sat, Jul 12, 2014 at 9:40 AM, Heiko Schocher hs@denx.de wrote:
add enable_spi_clk(), so board code can enable spi clocks.
Signed-off-by: Heiko Schocher hs@denx.de Cc: Eric Nelson eric.nelson@boundarydevices.com Cc: Stefano Babic sbabic@denx.de
- changes for v2:
- add comment from Stefano Babic:
- add comment for spi_num range
- add SPI_MAX_NUM in imx-regs.h
arch/arm/cpu/armv7/mx6/clock.c | 18 ++++++++++++++++++ arch/arm/include/asm/arch-mx6/clock.h | 1 + arch/arm/include/asm/arch-mx6/imx-regs.h | 1 + 3 files changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index bd65a08..799bd89 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -71,6 +71,24 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) } #endif
+/* spi_num can be from 0 - SPI_MAX_NUM */ +int enable_spi_clk(unsigned char enable, unsigned spi_num) +{
u32 reg;u32 mask;if (spi_num > SPI_MAX_NUM)return -EINVAL;mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);reg = __raw_readl(&imx_ccm->CCGR1);if (enable)reg |= mask;elsereg &= ~mask;__raw_writel(reg, &imx_ccm->CCGR1);return 0;+} static u32 decode_pll(enum pll_clocks pll, u32 infreq) { u32 div; diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 1b4ded7..339c789 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -57,6 +57,7 @@ void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); int enable_pcie_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(enum enet_freq freq); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 2135051..aa5bc92 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -405,6 +405,7 @@ struct cspi_regs { #define MXC_CSPICTRL_RXOVF (1 << 6) #define MXC_CSPIPERIOD_32KHZ (1 << 15) #define MAX_SPI_BYTES 32 +#define SPI_MAX_NUM 4
/* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN 18
1.8.3.1
Reviewed-by: Jagannadha Sutradharudu Teki jaganna@xilinx.com
I already picked the patch "spi_xchg_single" from this series, Shall I pick this on my tree?
thanks!