Use the full driver model GPIO and serial drivers in SPL now that these are supported. Since device tree is not available they will use platform data.
Remove the special SPL GPIO function as it is no longer needed.
This is all in one commit to maintain bisectability.
Signed-off-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: - Rebase on top of the SPI series
board/nvidia/seaboard/seaboard.c | 4 +--- drivers/gpio/Makefile | 4 ++++ drivers/gpio/tegra_gpio.c | 27 +++++++++++---------------- include/configs/tegra-common.h | 12 +++--------- 4 files changed, 19 insertions(+), 28 deletions(-)
diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 11472eb..25480e4 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -20,10 +20,8 @@ void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ -#ifndef CONFIG_SPL_BUILD gpio_request(GPIO_PI3, NULL); -#endif - tegra_spl_gpio_direction_output(GPIO_PI3, 0); + gpio_direction_output(GPIO_PI3, 0); } #endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index aa11f15..fe9a3b2 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -8,6 +8,10 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_DM_GPIO) += gpio-uclass.o endif +/* TODO(sjg@chromium.org): Only tegra supports driver model in SPL */ +ifdef CONFIG_TEGRA_GPIO +obj-$(CONFIG_DM_GPIO) += gpio-uclass.o +endif
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 88f7ef5..a1e51c0 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -131,21 +131,6 @@ static void set_level(unsigned gpio, int high) writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); }
-/* set GPIO pin 'gpio' as an output, with polarity 'value' */ -int tegra_spl_gpio_direction_output(int gpio, int value) -{ - /* Configure as a GPIO */ - set_config(gpio, 1); - - /* Configure GPIO output value. */ - set_level(gpio, value); - - /* Configure GPIO direction as output. */ - set_direction(gpio, 1); - - return 0; -} - /* * Generic_GPIO primitives. */ @@ -320,12 +305,19 @@ static int gpio_tegra_bind(struct udevice *parent) int bank_count; int bank; int ret; - int len;
/* If this is a child device, there is nothing to do here */ if (plat) return 0;
+ /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ +#ifdef CONFIG_SPL_BUILD + ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; + bank_count = TEGRA_GPIO_BANKS; +#else + { + int len; + /* * This driver does not make use of interrupts, other than to figure * out the number of GPIO banks @@ -335,6 +327,8 @@ static int gpio_tegra_bind(struct udevice *parent) bank_count = len / 3 / sizeof(u32); ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob, parent->of_offset, "reg"); + } +#endif for (bank = 0; bank < bank_count; bank++) { int port;
@@ -370,4 +364,5 @@ U_BOOT_DRIVER(gpio_tegra) = { .probe = gpio_tegra_probe, .priv_auto_alloc_size = sizeof(struct tegra_port_info), .ops = &gpio_tegra_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index d690045..1b01edc 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -19,13 +19,12 @@ #include <asm/arch/tegra.h> /* get chip and board defs */
#define CONFIG_DM +#define CONFIG_SPL_DM #define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#ifndef CONFIG_SPL_BUILD #define CONFIG_DM_SERIAL -#endif #define CONFIG_DM_SPI #define CONFIG_DM_SPI_FLASH +#define CONFIG_DM_GPIO
#define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE @@ -51,13 +50,7 @@ /* * NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#else #define CONFIG_TEGRA_SERIAL -#endif #define CONFIG_SYS_NS16550
/* @@ -141,6 +134,7 @@ GENERATED_GBL_DATA_SIZE)
#define CONFIG_TEGRA_GPIO + #define CONFIG_CMD_GPIO #define CONFIG_CMD_ENTERRCM