Refer to "Table 5-1. LS1 memory map" in "LS1 SoC Architecture Specification". It shows that: Start Address: 0x200000000 Size: 16MB DCSR
Or, see the dcsr node in arch/arm/boot/dts/ls1021a.dtsi in Linux.
Thanks, Chenhui ________________________________________ From: York Sun yorksun@freescale.com Sent: Tuesday, December 9, 2014 4:53 To: Wang Huan-B18965; u-boot@lists.denx.de; Jin Zhengxiong-R64188; Zhao Chenhui-B35336 Subject: Re: [PATCH v4 9/9] arm: ls102xa: Add NAND boot support for LS1021AQDS board
On 12/06/2014 06:46 AM, Alison Wang wrote:
This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha prabhakar@freescale.com Signed-off-by: Alison Wang alison.wang@freescale.com
Change log: v4: Use some defines instead of the magic numbers. v3: New file.
arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 ++ board/freescale/ls1021aqds/MAINTAINERS | 1 + board/freescale/ls1021aqds/ls1021aqds.c | 16 +++++ board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | 7 +++ configs/ls1021aqds_nand_defconfig | 4 ++ drivers/mtd/nand/fsl_ifc_spl.c | 10 ++++ include/configs/ls1021aqds.h | 72 +++++++++++++++++++++++ 8 files changed, 116 insertions(+) create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg create mode 100644 configs/ls1021aqds_nand_defconfig
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ba86eea..8318c91 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -13,6 +13,7 @@ #define OCRAM_SIZE 0x00020000
#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_DCSRBAR 0x20200000
This line is conflict with this patch http://patchwork.ozlabs.org/patch/402218/. Which one is correct?
York