Adds support for Bernecker & Rainer Industrieelektronik GmbH KWB Motherboard, using TI's AM3352 SoC.
Most of code is derived from TI's AM335x_EVM
Signed-off-by: Hannes Petermaier oe5hpm@oevsv.at Cc: trini@ti.com --- board/BuR/bur_kwb/Makefile | 16 ++ board/BuR/bur_kwb/am335xScreen.c | 548 ++++++++++++++++++++++++++++++++++++++ board/BuR/bur_kwb/am335xScreen.h | 45 ++++ board/BuR/bur_kwb/board.c | 522 ++++++++++++++++++++++++++++++++++++ board/BuR/bur_kwb/board.h | 18 ++ board/BuR/bur_kwb/mux.c | 213 +++++++++++++++ board/BuR/bur_kwb/u-boot.lds | 101 +++++++ boards.cfg | 1 + include/configs/bur_kwb.h | 352 ++++++++++++++++++++++++ 9 files changed, 1816 insertions(+) create mode 100644 board/BuR/bur_kwb/Makefile create mode 100644 board/BuR/bur_kwb/am335xScreen.c create mode 100644 board/BuR/bur_kwb/am335xScreen.h create mode 100644 board/BuR/bur_kwb/board.c create mode 100644 board/BuR/bur_kwb/board.h create mode 100644 board/BuR/bur_kwb/mux.c create mode 100644 board/BuR/bur_kwb/u-boot.lds create mode 100644 include/configs/bur_kwb.h
diff --git a/board/BuR/bur_kwb/Makefile b/board/BuR/bur_kwb/Makefile new file mode 100644 index 0000000..143708d --- /dev/null +++ b/board/BuR/bur_kwb/Makefile @@ -0,0 +1,16 @@ +# +# Makefile +# +# Copyright (C) 2014 Hannes Petermaier oe5hpm@oevsv.at - +# Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifeq ($(CONFIG_SPL_BUILD),y) +obj-y := mux.o +endif +ifeq ($(CONFIG_SYS_SCREEN),y) +obj-y += am335xScreen.o +endif +obj-y += board.o diff --git a/board/BuR/bur_kwb/am335xScreen.c b/board/BuR/bur_kwb/am335xScreen.c new file mode 100644 index 0000000..e491096 --- /dev/null +++ b/board/BuR/bur_kwb/am335xScreen.c @@ -0,0 +1,548 @@ +/* + * am335xScreen.c + * + * Copyright (C) 2013 Hannes Petermaier oe5hpm@oevsv.at + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Author(s) + * ========= + * Petermaier Hannes (hpm) hannes.petermaier@br-automation.com + * + * Description + * =========== + * this module uses the AM335x Framebuffer for writing out Characters on the + * given Display there is no need of any IRQ. + * for saving memory purpose only one framebuffer is used and this one is + * directly painted + * + * History + * ======= + * 17.12.2013 hpm created + * + * TODO: + * ===== + * check rasterCtrl Registers for supporting higher resolutions, only 480x272 + * is tested by now. + * + */ +#include <config.h> +#include <stdarg.h> +#include <malloc.h> +#include <vsprintf.h> +#include "am335xScreen.h" + +#if defined(CONFIG_SYS_SCREEN) && !defined(CONFIG_SPL_BUILD) + +#define DEBUG +#ifdef DEBUG +#define DBG(...) printf(__VA_ARGS__) +#else +#define DBG(...) +#endif /* DEBUG */ + +#define SCREEN_HMAX 1366 +#define SCREEN_VMAX 768 + +static const unsigned char char_tab2[257*8] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 126, 129, 165, 129, 189, 153, 129, 126, + 126, 255, 219, 255, 195, 231, 255, 126, + 108, 254, 254, 254, 124, 56, 16, 0, + 16, 56, 124, 254, 124, 56, 16, 0, + 56, 124, 56, 254, 254, 146, 16, 124, + 0, 16, 56, 124, 254, 124, 56, 124, + 0, 0, 24, 60, 60, 24, 0, 0, + + 255, 255, 231, 195, 195, 231, 255, 255, + 0, 60, 102, 66, 66, 102, 60, 0, + 255, 195, 153, 189, 189, 153, 195, 255, + 15, 7, 15, 125, 204, 204, 204, 120, + 60, 102, 102, 102, 60, 24, 126, 24, + 63, 51, 63, 48, 48, 112, 240, 224, + 127, 99, 127, 99, 99, 103, 230, 192, + 153, 90, 60, 231, 231, 60, 90, 153, + + 128, 224, 248, 254, 248, 224, 128, 0, + 2, 14, 62, 254, 62, 14, 2, 0, + 24, 60, 126, 24, 24, 126, 60, 24, + 102, 102, 102, 102, 102, 0, 102, 0, + 127, 219, 219, 123, 27, 27, 27, 0, + 62, 99, 56, 108, 108, 56, 134, 252, + 0, 0, 0, 0, 126, 126, 126, 0, + 24, 60, 126, 24, 126, 60, 24, 255, + + 24, 60, 126, 24, 24, 24, 24, 0, + 24, 24, 24, 24, 126, 60, 24, 0, + 0, 24, 12, 254, 12, 24, 0, 0, + 0, 48, 96, 254, 96, 48, 0, 0, + 0, 0, 192, 192, 192, 254, 0, 0, + 0, 36, 102, 255, 102, 36, 0, 0, + 0, 24, 60, 126, 255, 255, 0, 0, + 0, 255, 255, 126, 60, 24, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 24, 60, 60, 24, 24, 0, 24, 0, + 108, 108, 108, 0, 0, 0, 0, 0, + 108, 108, 254, 108, 254, 108, 108, 0, + 24, 126, 192, 124, 6, 252, 24, 0, + 0, 198, 204, 24, 48, 102, 198, 0, + 56, 108, 56, 118, 220, 204, 118, 0, + 48, 48, 96, 0, 0, 0, 0, 0, + 24, 48, 96, 96, 96, 48, 24, 0, + 96, 48, 24, 24, 24, 48, 96, 0, + 0, 102, 60, 255, 60, 102, 0, 0, + 0, 24, 24, 126, 24, 24, 0, 0, + 0, 0, 0, 0, 0, 24, 24, 48, + 0, 0, 0, 126, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 24, 24, 0, + 6, 12, 24, 48, 96, 192, 128, 0, + 124, 198, 214, 214, 214, 198, 124, 0, + 48, 112, 48, 48, 48, 48, 252, 0, + 120, 204, 12, 56, 96, 204, 252, 0, + 120, 204, 12, 56, 12, 204, 120, 0, + 28, 60, 108, 204, 254, 12, 30, 0, + 252, 192, 248, 12, 12, 204, 120, 0, + 56, 96, 192, 248, 204, 204, 120, 0, + 252, 204, 12, 24, 48, 48, 48, 0, + 120, 204, 204, 120, 204, 204, 120, 0, + 120, 204, 204, 124, 12, 24, 112, 0, + 0, 24, 24, 0, 0, 24, 24, 0, + 0, 24, 24, 0, 0, 24, 24, 48, + 24, 48, 96, 192, 96, 48, 24, 0, + 0, 0, 126, 0, 126, 0, 0, 0, + 96, 48, 24, 12, 24, 48, 96, 0, + 60, 102, 12, 24, 24, 0, 24, 0, + 124, 198, 222, 222, 220, 192, 124, 0, + 48, 120, 204, 204, 252, 204, 204, 0, + 252, 102, 102, 124, 102, 102, 252, 0, + 60, 102, 192, 192, 192, 102, 60, 0, + 248, 108, 102, 102, 102, 108, 248, 0, + 254, 98, 104, 120, 104, 98, 254, 0, + 254, 98, 104, 120, 104, 96, 240, 0, + 60, 102, 192, 192, 206, 102, 58, 0, + 204, 204, 204, 252, 204, 204, 204, 0, + 120, 48, 48, 48, 48, 48, 120, 0, + 30, 12, 12, 12, 204, 204, 120, 0, + 230, 102, 108, 120, 108, 102, 230, 0, + 240, 96, 96, 96, 98, 102, 254, 0, + 198, 238, 254, 254, 214, 198, 198, 0, + 198, 230, 246, 222, 206, 198, 198, 0, + 56, 108, 198, 198, 198, 108, 56, 0, + 252, 102, 102, 124, 96, 96, 240, 0, + 124, 198, 198, 198, 214, 124, 14, 0, + 252, 102, 102, 124, 108, 102, 230, 0, + 124, 198, 224, 120, 14, 198, 124, 0, + 252, 180, 48, 48, 48, 48, 120, 0, + 204, 204, 204, 204, 204, 204, 252, 0, + 204, 204, 204, 204, 204, 120, 48, 0, + 198, 198, 198, 198, 214, 254, 108, 0, + 198, 198, 108, 56, 108, 198, 198, 0, + 204, 204, 204, 120, 48, 48, 120, 0, + 254, 198, 140, 24, 50, 102, 254, 0, + 120, 96, 96, 96, 96, 96, 120, 0, + 192, 96, 48, 24, 12, 6, 2, 0, + 120, 24, 24, 24, 24, 24, 120, 0, + 16, 56, 108, 198, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 255, + 48, 48, 24, 0, 0, 0, 0, 0, + 0, 0, 120, 12, 124, 204, 118, 0, + 224, 96, 96, 124, 102, 102, 220, 0, + 0, 0, 120, 204, 192, 204, 120, 0, + 28, 12, 12, 124, 204, 204, 118, 0, + 0, 0, 120, 204, 252, 192, 120, 0, + 56, 108, 100, 240, 96, 96, 240, 0, + 0, 0, 118, 204, 204, 124, 12, 248, + 224, 96, 108, 118, 102, 102, 230, 0, + 48, 0, 112, 48, 48, 48, 120, 0, + 12, 0, 28, 12, 12, 204, 204, 120, + 224, 96, 102, 108, 120, 108, 230, 0, + 112, 48, 48, 48, 48, 48, 120, 0, + 0, 0, 204, 254, 254, 214, 214, 0, + 0, 0, 184, 204, 204, 204, 204, 0, + 0, 0, 120, 204, 204, 204, 120, 0, + 0, 0, 220, 102, 102, 124, 96, 240, + 0, 0, 118, 204, 204, 124, 12, 30, + 0, 0, 220, 118, 98, 96, 240, 0, + 0, 0, 124, 192, 112, 28, 248, 0, + 16, 48, 252, 48, 48, 52, 24, 0, + 0, 0, 204, 204, 204, 204, 118, 0, + 0, 0, 204, 204, 204, 120, 48, 0, + 0, 0, 198, 198, 214, 254, 108, 0, + 0, 0, 198, 108, 56, 108, 198, 0, + 0, 0, 204, 204, 204, 124, 12, 248, + 0, 0, 252, 152, 48, 100, 252, 0, + 28, 48, 48, 224, 48, 48, 28, 0, + 24, 24, 24, 0, 24, 24, 24, 0, + 224, 48, 48, 28, 48, 48, 224, 0, + 118, 220, 0, 0, 0, 0, 0, 0, + 0, 16, 56, 108, 198, 198, 254, 0, + 124, 198, 192, 198, 124, 12, 6, 124, + 0, 204, 0, 204, 204, 204, 118, 0, + 28, 0, 120, 204, 252, 192, 120, 0, + 126, 129, 60, 6, 62, 102, 59, 0, + 204, 0, 120, 12, 124, 204, 118, 0, + 224, 0, 120, 12, 124, 204, 118, 0, + 48, 48, 120, 12, 124, 204, 118, 0, + 0, 0, 124, 198, 192, 120, 12, 56, + 126, 129, 60, 102, 126, 96, 60, 0, + 204, 0, 120, 204, 252, 192, 120, 0, + 224, 0, 120, 204, 252, 192, 120, 0, + 204, 0, 112, 48, 48, 48, 120, 0, + 124, 130, 56, 24, 24, 24, 60, 0, + 224, 0, 112, 48, 48, 48, 120, 0, + 198, 16, 124, 198, 254, 198, 198, 0, + 48, 48, 0, 120, 204, 252, 204, 0, + 28, 0, 252, 96, 120, 96, 252, 0, + 0, 0, 127, 12, 127, 204, 127, 0, + 62, 108, 204, 254, 204, 204, 206, 0, + 120, 132, 0, 120, 204, 204, 120, 0, + 0, 204, 0, 120, 204, 204, 120, 0, + 0, 224, 0, 120, 204, 204, 120, 0, + 120, 132, 0, 204, 204, 204, 118, 0, + 0, 224, 0, 204, 204, 204, 118, 0, + 0, 204, 0, 204, 204, 124, 12, 248, + 195, 24, 60, 102, 102, 60, 24, 0, + 204, 0, 204, 204, 204, 204, 120, 0, + 24, 24, 126, 192, 192, 126, 24, 24, + 56, 108, 100, 240, 96, 230, 252, 0, + 204, 204, 120, 48, 252, 48, 252, 48, + 248, 204, 204, 250, 198, 207, 198, 195, + 14, 27, 24, 60, 24, 24, 216, 112, + 28, 0, 120, 12, 124, 204, 118, 0, + 56, 0, 112, 48, 48, 48, 120, 0, + 0, 28, 0, 120, 204, 204, 120, 0, + 0, 28, 0, 204, 204, 204, 118, 0, + 0, 248, 0, 184, 204, 204, 204, 0, + 252, 0, 204, 236, 252, 220, 204, 0, + 60, 108, 108, 62, 0, 126, 0, 0, + 56, 108, 108, 56, 0, 124, 0, 0, + 24, 0, 24, 24, 48, 102, 60, 0, + 0, 0, 0, 252, 192, 192, 0, 0, + 0, 0, 0, 252, 12, 12, 0, 0, + 198, 204, 216, 54, 107, 194, 132, 15, + 195, 198, 204, 219, 55, 109, 207, 3, + 24, 0, 24, 24, 60, 60, 24, 0, + 0, 51, 102, 204, 102, 51, 0, 0, + 0, 204, 102, 51, 102, 204, 0, 0, + 34, 136, 34, 136, 34, 136, 34, 136, + 85, 170, 85, 170, 85, 170, 85, 170, + 221, 119, 221, 119, 221, 119, 221, 119, + 24, 24, 24, 24, 24, 24, 24, 24, + 24, 24, 24, 24, 248, 24, 24, 24, + 24, 24, 248, 24, 248, 24, 24, 24, + 54, 54, 54, 54, 246, 54, 54, 54, + 0, 0, 0, 0, 254, 54, 54, 54, + 0, 0, 248, 24, 248, 24, 24, 24, + 54, 54, 246, 6, 246, 54, 54, 54, + 54, 54, 54, 54, 54, 54, 54, 54, + 0, 0, 254, 6, 246, 54, 54, 54, + 54, 54, 246, 6, 254, 0, 0, 0, + 54, 54, 54, 54, 254, 0, 0, 0, + 24, 24, 248, 24, 248, 0, 0, 0, + 0, 0, 0, 0, 248, 24, 24, 24, + 24, 24, 24, 24, 31, 0, 0, 0, + 24, 24, 24, 24, 255, 0, 0, 0, + 0, 0, 0, 0, 255, 24, 24, 24, + 24, 24, 24, 24, 31, 24, 24, 24, + 0, 0, 0, 0, 255, 0, 0, 0, + 24, 24, 24, 24, 255, 24, 24, 24, + 24, 24, 31, 24, 31, 24, 24, 24, + 54, 54, 54, 54, 55, 54, 54, 54, + 54, 54, 55, 48, 63, 0, 0, 0, + 0, 0, 63, 48, 55, 54, 54, 54, + 54, 54, 247, 0, 255, 0, 0, 0, + 0, 0, 255, 0, 247, 54, 54, 54, + 54, 54, 55, 48, 55, 54, 54, 54, + 0, 0, 255, 0, 255, 0, 0, 0, + 54, 54, 247, 0, 247, 54, 54, 54, + 24, 24, 255, 0, 255, 0, 0, 0, + 54, 54, 54, 54, 255, 0, 0, 0, + 0, 0, 255, 0, 255, 24, 24, 24, + 0, 0, 0, 0, 255, 54, 54, 54, + 54, 54, 54, 54, 63, 0, 0, 0, + 24, 24, 31, 24, 31, 0, 0, 0, + 0, 0, 31, 24, 31, 24, 24, 24, + 0, 0, 0, 0, 63, 54, 54, 54, + 54, 54, 54, 54, 255, 54, 54, 54, + 24, 24, 255, 24, 255, 24, 24, 24, + 24, 24, 24, 24, 248, 0, 0, 0, + 0, 0, 0, 0, 31, 24, 24, 24, + 255, 255, 255, 255, 255, 255, 255, 255, + 0, 0, 0, 0, 255, 255, 255, 255, + 240, 240, 240, 240, 240, 240, 240, 240, + 15, 15, 15, 15, 15, 15, 15, 15, + 255, 255, 255, 255, 0, 0, 0, 0, + 0, 0, 118, 220, 200, 220, 118, 0, + 124, 198, 198, 204, 198, 195, 206, 0, + 0, 252, 204, 192, 192, 192, 192, 0, + 0, 0, 254, 108, 108, 108, 108, 0, + 252, 204, 96, 48, 96, 204, 252, 0, + 0, 0, 126, 216, 216, 216, 112, 0, + 0, 102, 102, 102, 102, 124, 96, 192, + 0, 118, 220, 24, 24, 24, 24, 0, + 252, 48, 120, 204, 204, 120, 48, 252, + 56, 108, 198, 254, 198, 108, 56, 0, + 56, 108, 198, 198, 108, 108, 238, 0, + 28, 48, 24, 124, 204, 204, 120, 0, + 0, 0, 126, 219, 219, 126, 0, 0, + 6, 12, 126, 219, 219, 126, 96, 192, + 56, 96, 192, 248, 192, 96, 56, 0, + 120, 204, 204, 204, 204, 204, 204, 0, + 0, 126, 0, 126, 0, 126, 0, 0, + 24, 24, 126, 24, 24, 0, 126, 0, + 96, 48, 24, 48, 96, 0, 252, 0, + 24, 48, 96, 48, 24, 0, 252, 0, + 14, 27, 27, 24, 24, 24, 24, 24, + 24, 24, 24, 24, 24, 216, 216, 112, + 24, 24, 0, 126, 0, 24, 24, 0, + 0, 118, 220, 0, 118, 220, 0, 0, + 56, 108, 108, 56, 0, 0, 0, 0, + 0, 0, 0, 24, 24, 0, 0, 0, + 0, 0, 0, 0, 24, 0, 0, 0, + 15, 12, 12, 12, 236, 108, 60, 28, + 88, 108, 108, 108, 108, 0, 0, 0, + 112, 152, 48, 96, 248, 0, 0, 0, + 0, 0, 60, 60, 60, 60, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +struct lcdhw_typ { + unsigned int pid; /* 0x00 */ + unsigned int ctrl; /* 0x04 */ + unsigned int gap0; /* 0x08 */ + unsigned int lidd_ctrl; /* 0x0C */ + unsigned int lidd_cs0_conf; /* 0x10 */ + unsigned int lidd_cs0_addr; /* 0x14 */ + unsigned int lidd_cs0_data; /* 0x18 */ + unsigned int lidd_cs1_conf; /* 0x1C */ + unsigned int lidd_cs1_addr; /* 0x20 */ + unsigned int lidd_cs1_data; /* 0x24 */ + unsigned int raster_ctrl; /* 0x28 */ + unsigned int raster_timing0; /* 0x2C */ + unsigned int raster_timing1; /* 0x30 */ + unsigned int raster_timing2; /* 0x34 */ + unsigned int raster_subpanel; /* 0x38 */ + unsigned int raster_subpanel2; /* 0x3C */ + unsigned int lcddma_ctrl; /* 0x40 */ + unsigned int lcddma_fb0_base; /* 0x44 */ + unsigned int lcddma_fb0_ceiling; /* 0x48 */ + unsigned int lcddma_fb1_base; /* 0x4C */ + unsigned int lcddma_fb1_ceiling; /* 0x50 */ + unsigned int sysconfig; /* 0x54 */ + unsigned int irqstatus_raw; /* 0x58 */ + unsigned int irqstatus; /* 0x5C */ + unsigned int irqenable_set; /* 0x60 */ + unsigned int irqenable_clear; /* 0x64 */ + unsigned int gap1; /* 0x68 */ + unsigned int clkc_enable; /* 0x6C */ + unsigned int clkc_reset; /* 0x70 */ +}; + +struct screen_typ { + /* hw structure of AM335x LCD-Controller */ + struct lcdhw_typ *plcdhw; + /* pointer to the LCD timing configuration */ + struct lcdsetting_typ *plcdsettings; + /* framebuffer of the LCD-device */ + void *pfb; + /* size of 1 character in pixels */ + unsigned int fontsize; + /* resolution of framebuffer */ + unsigned int resx, resy; + /* size of frambebuffer */ + unsigned int fbsize; + /* actual position of 'cursor' */ + unsigned int cursx, cursy; +}; + +static struct screen_typ screen; + +static void setPix(struct screen_typ *pscr, + unsigned int x, unsigned int y, unsigned int color) +{ + unsigned int addroffset = 0; + + /* braces not for function, only for better reading by human :-) */ + addroffset = y * (pscr->resx*4) + (x*4); + *(unsigned int *)(pscr->pfb+addroffset) = (color & 0x00FFFFFF); +} +static void outch(struct screen_typ *pscr, + unsigned int x, unsigned int y, + unsigned int clr, char ch) +{ + unsigned char i, k; + unsigned char maske; + + for (i = 0; i < 8; i++) { + maske = char_tab2[ch*8+i]; + for (k = 0; k <= 7; k++) { + if (maske & 0x80) + setPix(pscr, x+k, y+i, clr); + maske = maske << 1; + } + } +} +static int printScr(struct screen_typ *pscr, char *str) +{ + int cnt = 0; + + if (0 != pscr && 0 != str) { + while (*str != 0) { + if ('\r' == *str) { + pscr->cursx = 0; + } else if ('\n' == *str) { + pscr->cursy += pscr->fontsize; + pscr->cursx = 0; + if (pscr->cursx > pscr->resy) + pscr->cursy = pscr->resy-pscr->fontsize; + } else { + outch(pscr, pscr->cursx, pscr->cursy, + 0x00FFFFFF, *str); + pscr->cursx += pscr->fontsize; + if (pscr->cursx > pscr->resx) + pscr->cursx = pscr->resx-pscr->fontsize; + } + str++; + cnt++; + } + return cnt; + } + return -1; +} +static int setupLCD(struct screen_typ *pscr) +{ + struct lcdhw_typ *phwlcd = (struct lcdhw_typ *)pscr->plcdhw; + + DBG("setting up LCD-Controller for %dx%d (hfp=%d, hbp=%d, hsw=%d / ", + pscr->plcdsettings->hactive, pscr->plcdsettings->vactive, + pscr->plcdsettings->hfp, + pscr->plcdsettings->hbp, + pscr->plcdsettings->hsync); + + DBG("vfp=%d, vbp=%d, vsw=%d / clk-div=%d)\n", + pscr->plcdsettings->vfp, + pscr->plcdsettings->vbp, + pscr->plcdsettings->vsync, + pscr->plcdsettings->lcdclkdiv); + + + phwlcd->clkc_enable = 0x07; + + phwlcd->raster_ctrl = 0; + phwlcd->ctrl = (pscr->plcdsettings->lcdclkdiv << 8) | 0x01; + + phwlcd->lcddma_fb0_base = (unsigned int) pscr->pfb; + phwlcd->lcddma_fb0_ceiling = (unsigned int) pscr->pfb+pscr->fbsize; + phwlcd->lcddma_fb1_base = (unsigned int) pscr->pfb; + phwlcd->lcddma_fb1_ceiling = (unsigned int) pscr->pfb+pscr->fbsize; + phwlcd->lcddma_ctrl = 0x40; + phwlcd->raster_timing0 = ((pscr->plcdsettings->hbp-1) << 24) | + ((pscr->plcdsettings->hfp-1) << 16) | + ((pscr->plcdsettings->hsync-1) << 10) | + (((pscr->plcdsettings->hactive >> 4)-1) << 4); + phwlcd->raster_timing1 = (pscr->plcdsettings->vbp << 24) | + (pscr->plcdsettings->vfp << 16) | + ((pscr->plcdsettings->vsync-1) << 10) | + ((pscr->plcdsettings->vactive-1) << 0); + phwlcd->raster_timing2 = 0x0230FF00; + + DBG("starting LCD-Controller.\n"); + phwlcd->raster_ctrl = 0x06000081; + + /* lcd-on */ + if (0 != pscr->plcdsettings->ppwrfct) + pscr->plcdsettings->ppwrfct(1); + + return 0; +} +int drawrecticle(unsigned int x, unsigned int y, + unsigned int w, unsigned int h, unsigned int color) +{ + int i, j; + + for (i = y; i < y+h; i++) { + for (j = x; j < x+w; j++) + setPix(&screen, j, i, color); + } +} +int prints(const char *fmt, ...) +{ + va_list args; + char printbuffer[CONFIG_SYS_PBSIZE]; + + va_start(args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + vsprintf(printbuffer, fmt, args); + va_end(args); + + /* Print the string */ + return printScr(&screen, printbuffer); +} +int printsxy(unsigned int x, unsigned int y, const char *fmt, ...) +{ + va_list args; + unsigned int xrestore = x; + unsigned int yrestore = y; + char printbuffer[CONFIG_SYS_PBSIZE]; + + screen.cursx = x; + screen.cursy = y; + + va_start(args, fmt); + + /* For this to work, printbuffer must be larger than + * anything we ever want to print. + */ + vsprintf(printbuffer, fmt, args); + va_end(args); + + /* Print the string */ + printScr(&screen, printbuffer); + + screen.cursx = xrestore; + screen.cursy = yrestore; + + return 0; +} +int setupscreen(void *phwbase, struct lcdsetting_typ *plcdset, void *pfb) +{ + if (0 != phwbase && + 0 != plcdset && + plcdset->hactive >= 0 && plcdset->hactive <= SCREEN_HMAX && + plcdset->vactive >= 0 && plcdset->vactive <= SCREEN_VMAX + ) { + screen.plcdhw = phwbase; + screen.resx = plcdset->hactive; + screen.resy = plcdset->vactive; + screen.fbsize = plcdset->hactive*plcdset->vactive*4+0x20; + screen.fontsize = 8; + screen.plcdsettings = (struct lcdsetting_typ *)plcdset; + + if (0 != pfb) { + screen.pfb = pfb; + } else { + screen.pfb = malloc(screen.fbsize); + if (0 == screen.pfb) { + printf("ERROR: no suitable Framebuffer!\n"); + return -1; + } + } + + DBG("using fb (0x%08x) with size %d\n", + (unsigned int) screen.pfb, screen.fbsize); + memset(screen.pfb, 0x00, screen.fbsize); + *(unsigned int *)screen.pfb = 0x4000; + setupLCD(&screen); + /* point to display data, palette is up to 0x20 */ + screen.pfb += 0x20; + + return 0; + } + return -1; +} +#endif /* CONFIG_SYS_SCREEN */ diff --git a/board/BuR/bur_kwb/am335xScreen.h b/board/BuR/bur_kwb/am335xScreen.h new file mode 100644 index 0000000..d76a3b8 --- /dev/null +++ b/board/BuR/bur_kwb/am335xScreen.h @@ -0,0 +1,45 @@ +/* + * am335xScreen.h + * + * Copyright (C) 2013 Hannes Petermaier oe5hpm@oevsv.at + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Author(s) + * ========= + * Petermaier Hannes (hpm) hannes.petermaier@br-automation.com + * + * History + * ======= + * 17.12.2013 hpm created + * + */ +#ifndef __AM335XSCREEN_H__ +#define __AM335XSCREEN_H__ + +struct lcdsetting_typ { + unsigned int hactive; /* number of pixels per line */ + unsigned int hfp; /* horizontal front-porch */ + unsigned int hbp; /* horizontal back-porch */ + unsigned int hsync; /* horizontal sync-width */ + + unsigned int vactive; /* number of lines */ + unsigned int vfp; /* vertical front-porch */ + unsigned int vbp; /* vertical back-porch */ + unsigned int vsync; /* vertical sync-width */ + + /* divisor of LCDPLL-Clk for generating Pixelclock */ + unsigned int lcdclkdiv; + + /* pointer to a function for switching LCD On/Off */ + void (*ppwrfct)(int); + /* pointer to a function for switching BKL On/Off */ + void (*pbklfct)(int); +}; + +int setupscreen(void *phwbase, struct lcdsetting_typ *plcdset, void *pfb); +int prints(const char *fmt, ...); +int printsxy(unsigned int x, unsigned int y, const char *fmt, ...); + +#endif diff --git a/board/BuR/bur_kwb/board.c b/board/BuR/bur_kwb/board.c new file mode 100644 index 0000000..5a1b15f --- /dev/null +++ b/board/BuR/bur_kwb/board.c @@ -0,0 +1,522 @@ +/* + * board.c + * + * Board functions for B&R KWB Board + * + * Copyright (C) 2013 Hannes Petermaier oe5hpm@oevsv.at + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Author(s) + * ========= + * Petermaier Hannes (hpm) hannes.petermaier@br-automation.com + * + * History + * ======= + * xx.10.2013 hpm - created, adopted from ti_am335x_evm + * 06.12.2013 hpm - setting MPU_PLL to 600 MHz (as required for + * industrial) + * - implemented simple boot-mode detection + * - reduced resetpulse for USB2SD controller + * from 5ms to 1ms + * 10.12.2013 hpm - switch OFF LCD-Screen within SPL-Stage + * (due to invalid 3V3 pullup resistor) + * - powerUP 3V3 via I2C-Resetcontroller within SPL-Stage + * 16.12.2013 hpm - V1.10: changed bootaddr of VxWorks from + * 0x82000000 to 0x80100000 + * 24.12.2013 hpm - V1.11: added LCD-support + * 30.01.2014 hpm - V2.00: ported to new U-Boot (2014) sources + * + */ +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include <i2c.h> +#include <miiphy.h> +#include <cpsw.h> +#include <power/tps65217.h> +#include <power/tps65910.h> +#include "board.h" +#include "am335xScreen.h" + +DECLARE_GLOBAL_DATA_PTR; + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +/* -------------------------------------------------------------------------*/ +/* -- defines for used GPIO Hardware -- */ +#define KEY (0+4) +#define LCD_PWR (0+5) +#define PUSH_KEY (0+31) +#define USB2SD_NRST (32+29) +#define USB2SD_PWR (96+13) +/* -------------------------------------------------------------------------*/ +/* -- PSOC Resetcontroller Register defines -- */ + +/* I2C Address of controller */ +#define RSTCTRL_ADDR 0x75 +/* Register for CTRL-word */ +#define RSTCTRL_CTRLREG 0x01 +/* Register for giving some information to VxWorks OS */ +#define RSTCTRL_SCRATCHREG 0x04 + +/* -- defines for RSTCTRL_CTRLREG -- */ +#define RSTCTRL_FORCE_PWR_NEN 0x0404 + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_SCREEN) +void lcdpower(int onoff) +{ + if (onoff) + gpio_set_value(LCD_PWR, 1); + else + gpio_set_value(LCD_PWR, 0); +} +static struct lcdsetting_typ lcdsetting = { + .ppwrfct = &lcdpower, + .hactive = 480, + .hfp = 8, + .hbp = 43, + .hsync = 2, + .vactive = 272, + .vfp = 4, + .vbp = 2, + .vsync = 10, + .lcdclkdiv = 21 /* results in 192/21 = 9.1428 MHz */ +}; +#endif /* CONFIG_SPL_BUILD, ... */ + +#if defined(CONFIG_SPL_BUILD) +/* TODO: check ram-timing ! */ +static const struct ddr_data ddr3_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, +}; +static const struct cmd_control ddr3_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; +static struct emif_regs ddr3_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, +}; +const struct ctrl_ioregs ddr3_ioregs = { + .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, + .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, +}; +#ifdef CONFIG_SPL_OS_BOOT +/* + * ---------------------------------------------------------------------------- + * called from spl_nand.c + * return 0 for loading linux, return 1 for loading u-boot + */ +int spl_start_uboot(void) +{ + return 1; +} +#endif + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr3 = { + 400, OSC-1, 1, -1, -1, -1, -1}; + +void am33xx_spl_board_init(void) +{ + int mpu_vdd; + int usb_cur_lim; + unsigned int oldspeed; + unsigned short buf; + + /* setup I2C */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + + /* power-OFF LCD-Display */ + gpio_direction_output(LCD_PWR, 0); + + /* power-ON 3V3 via Resetcontroller */ + oldspeed = i2c_get_bus_speed(); + i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC); + buf = RSTCTRL_FORCE_PWR_NEN; + i2c_write(RSTCTRL_ADDR, RSTCTRL_CTRLREG, 1, + (uint8_t *)&buf, sizeof(buf)); + i2c_set_bus_speed(oldspeed); + +#if defined(CONFIG_AM335X_USB0) + /* power on USB2SD Controller */ + gpio_direction_output(USB2SD_PWR, 1); + mdelay(1); + /* give a reset Pulse to USB2SD Controller */ + gpio_direction_output(USB2SD_NRST, 0); + mdelay(1); + gpio_set_value(USB2SD_NRST, 1); +#endif + /* Get the frequency */ + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + printf("detected max. frequency: %d - ", dpll_mpu_opp100.m); + + if (i2c_probe(TPS65217_CHIP_PM)) { + printf("PMIC (0x%02x) not found! skip further initalization.\n", + TPS65217_CHIP_PM); + return; + } + + /* + * for testing purpose tune up AM3352 to 1GHz, + * in series production we have to reduce downto 600 MHz + */ + dpll_mpu_opp100.m = MPUPLL_M_1000; + printf("retuning MPU-PLL to: %d MHz.\n", dpll_mpu_opp100.m); + /* + * Increase USB current limit to 1300mA or 1800mA and set + * the MPU voltage controller as needed. + */ + if (dpll_mpu_opp100.m == MPUPLL_M_1000) { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; + } else { + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; + } + + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH, + usb_cur_lim, TPS65217_USB_INPUT_CUR_LIMIT_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set DCDC3 (CORE) voltage to 1.125V */ + if (tps65217_voltage_update(TPS65217_DEFDCDC3, + TPS65217_DCDC_VOLT_SEL_1125MV)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set CORE Frequencies to OPP100 */ + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); + + /* Set DCDC2 (MPU) voltage */ + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { + puts("tps65217_voltage_update failure\n"); + return; + } + + /* Set LDO3 to 1.8V */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS1, + TPS65217_LDO_VOLTAGE_OUT_1_8, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + /* Set LDO4 to 3.3V */ + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, + TPS65217_DEFLS2, + TPS65217_LDO_VOLTAGE_OUT_3_3, + TPS65217_LDO_MASK)) + puts("tps65217_reg_write failure\n"); + + /* Set MPU Frequency to what we detected now that voltages are set */ + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); +} + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr3; +} + +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + config_ddr(400, &ddr3_ioregs, + &ddr3_data, + &ddr3_cmd_ctrl_data, + &ddr3_emif_reg_data, 0); +} +#endif /* CONFIG_SPL_BUILD */ + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gpmc_init(); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + const unsigned int ton = 250; + const unsigned int toff = 1000; + unsigned int cnt = 3; + unsigned short buf = 0xAAAA; + unsigned int oldspeed; + + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL2, 0x32, 0xFF); /* 50% dimlevel */ + + if (gpio_get_value(KEY)) { + do { + /* turn on light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x09, 0xFF); + mdelay(ton); + /* turn off light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x01, 0xFF); + mdelay(toff); + cnt--; + if (!gpio_get_value(KEY) && + gpio_get_value(PUSH_KEY) && 1 == cnt) { + printf("updating from USB ...\n"); + setenv("bootcmd", "run updateUSB"); + break; + } else if (!gpio_get_value(KEY)) { + break; + } + } while (cnt); + } + + switch (cnt) { + case 0: + printf("3 blinks ... entering BOOT mode.\n"); + buf = 0x0000; + break; + case 1: + printf("2 blinks ... entering DIAGNOSE mode.\n"); + buf = 0x0F0F; + break; + case 2: + printf("1 blinks ... entering SERVICE mode.\n"); + buf = 0xB4B4; + break; + case 3: + printf("0 blinks ... entering RUN mode.\n"); + buf = 0x0404; + break; + } + mdelay(ton); + /* turn on light */ + tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, + TPS65217_WLEDCTRL1, 0x09, 0xFF); + /* write bootinfo into scratchregister of resetcontroller */ + oldspeed = i2c_get_bus_speed(); + i2c_set_bus_speed(CONFIG_SYS_OMAP24_I2C_SPEED_PSOC); + i2c_write(RSTCTRL_ADDR, RSTCTRL_SCRATCHREG, 1, + (uint8_t *)&buf, sizeof(buf)); + i2c_set_bus_speed(oldspeed); + +#if defined(CONFIG_SYS_SCREEN) && !defined(CONFIG_SPL_BUILD) + int x, y, size; + + if (0 == setupscreen((void *)LCD_CNTL_BASE, &lcdsetting, 0)) { + prints("Bernecker & Rainer Industrieelektronik GmbH\n"); + printsxy(0, 264, "booting ... please wait."); + + x = 10; + y = 10; + size = 82; + + drawrecticle(x, y, size, size, 0x00aaaaaa); + printsxy(x+10, y+10, "0xAA"); + x += (size + 10); + + drawrecticle(x, y, size, size, 0x007f7f7f); + printsxy(x+10, y+10, "0x7F"); + x += (size + 10); + + drawrecticle(x, y, size, size, 0x007a7a7a); + printsxy(x+10, y+10, "0x7A"); + x += (size + 10); + + drawrecticle(x, y, size, size, 0x00999999); + printsxy(x+10, y+10, "0x99"); + x += (size + 10); + + drawrecticle(x, y, size, size, 0x00ff0000); + printsxy(x+10, y+10, "red"); + x = 10; + y += (size + 10); + + /* --- */ + drawrecticle(x, y, size, size, 0x00d9d9d9); + printsxy(x+10, y+10, "0xD9"); + x += (size + 10); + + drawrecticle(x, y, size, size, 0x00e6e6e6); + printsxy(x+10, y+10, "0xE6"); + x += (size + 10); + + drawrecticle(x, y, size, size, 0x00dedede); + printsxy(x+10, y+10, "0xDE"); + x += (size + 10); + + drawrecticle(x, y, size, size, 0x004d4d4d); + printsxy(x+10, y+10, "0x4D"); + x += (size + 10); + + drawrecticle(x, y, size, size, 0x000000ff); + printsxy(x+10, y+10, "blue"); + x = 10; + y += (size + 10); + + /* --- */ + x += (size + 10); + x += (size + 10); + x += (size + 10); + x += (size + 10); + drawrecticle(x, y, size, size, 0x0000ff00); + printsxy(x+10, y+10, "green"); + } else { + printf("no suitable display-layer!\n"); + } +#endif /* CONFIG_SYS_SCREEN */ +#if _RTCTEST + int year, mon, d, h, min; + + printf("echo setting PMIC Register in the RTC.\n"); + *(unsigned int *)0x44e3e098 = 0x1f010; + printf("read back PMIC Register: 0x%08x\n", + *(unsigned int *)0x44e3e098); + + year = *(unsigned int *)0x44e3e014; + mon = *(unsigned int *)0x44e3e010; + d = *(unsigned int *)0x44e3e00C; + h = *(unsigned int *)0x44e3e008; + min = *(unsigned int *)0x44e3e004; + printf("power off event in 2min from now (%d-%d-%d / %d:%d).\n", + year, min, d, h, min); + + *(unsigned int *)0x44e3e094 = year; + *(unsigned int *)0x44e3e090 = mon; + *(unsigned int *)0x44e3e08c = d; + *(unsigned int *)0x44e3e088 = h; + *(unsigned int *)0x44e3e084 = min+2; + + *(unsigned int *)0x44e3e048 = 0x10; + *(unsigned int *)0x44e3e040 = 1; + printf("ok ... waiting for tomorrow :-)\n"); +#endif /* _RTCTEST */ + return 0; +} +#endif /* CONFIG_BOARD_LATE_INIT */ + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif /* CONFIG_DRIVER_TI_CPSW, ... */ + +#if defined(CONFIG_DRIVER_TI_CPSW) +int board_eth_init(bd_t *bis) +{ + int rv = 0; + uint8_t mac_addr[6]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + if (!getenv("ethaddr")) { + printf("<ethaddr> not set. Validating first E-fuse MAC ... "); + + if (is_valid_ether_addr(mac_addr)) { + printf("using: %02X:%02X:%02X:%02X:%02X:%02X.\n", + mac_addr[0], mac_addr[1], mac_addr[2], + mac_addr[3], mac_addr[4], mac_addr[5] + ); + eth_setenv_enetaddr("ethaddr", mac_addr); + } + } + writel(MII_MODE_ENABLE, &cdev->miisel); + cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; + cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; + + rv = cpsw_register(&cpsw_data); + if (rv < 0) { + printf("Error %d registering CPSW switch\n", rv); + return 0; + } +#endif /* CONFIG_DRIVER_TI_CPSW, ... */ + return rv; +} +#endif /* CONFIG_DRIVER_TI_CPSW */ diff --git a/board/BuR/bur_kwb/board.h b/board/BuR/bur_kwb/board.h new file mode 100644 index 0000000..def41aa --- /dev/null +++ b/board/BuR/bur_kwb/board.h @@ -0,0 +1,18 @@ +/* + * board.h + * + * BUR-KWB boards information header + * + * Copyright (C) 2013, Bernecker & Rainer Industrieelektronik GmbH - + * http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/BuR/bur_kwb/mux.c b/board/BuR/bur_kwb/mux.c new file mode 100644 index 0000000..da4b9f3 --- /dev/null +++ b/board/BuR/bur_kwb/mux.c @@ -0,0 +1,213 @@ +/* + * mux.c + * + * Pinmux Setting for B&R LEIT Board(s) + * + * Copyright (C) 2013 Hannes Petermaier oe5hpm@oevsv.at + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "board.h" + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_id), (MODE(0) | RXACTIVE)}, + /* USB0 DrvBus Receiver disable (from romcode 0x20) */ + {OFFSET(usb0_drvvbus), (MODE(0))}, + /* USB1 DrvBus as GPIO due to HW-Workaround */ + {OFFSET(usb1_drvvbus), (MODE(7))}, + {-1}, +}; +#ifdef CONFIG_AM335X_USB1 +static struct module_pin_mux usb1_pin_mux[] = { + /* USB1 DrvBus Receiver disable (from romcode 0x20) */ + {OFFSET(usb1_drvvbus), (MODE(0))}, + /* USB1 VBUS pulldown (to detect hostmode) */ + {OFFSET(usb1_vbus), (MODE(0) | PULLUP_EN)}, + /* + * GPIO1_29 (GPMC_nCS0) has to be driven high + * for releasing nRESET of USB2SD adapter + */ + {OFFSET(gpmc_csn0), (MODE(7))}, + {-1}, +}; +#endif +static struct module_pin_mux spi1_pin_mux[] = { + /* SPI1_SCLK */ + {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_D0 */ + {OFFSET(mcasp0_fsx), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_D1 */ + {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE}, + /* SPI1_CS0 */ + {OFFSET(mcasp0_ahclkr), MODE(3) | PULLUDEN | PULLUP_EN | RXACTIVE}, + {-1}, +}; +static struct module_pin_mux dcan0_pin_mux[] = { + /* DCAN0 TX */ + {OFFSET(uart1_ctsn), MODE(2) | PULLUDEN | PULLUP_EN}, + /* DCAN0 RX */ + {OFFSET(uart1_rtsn), MODE(2) | RXACTIVE}, + {-1}, +}; +static struct module_pin_mux dcan1_pin_mux[] = { + /* DCAN1 TX */ + {OFFSET(uart1_rxd), MODE(2) | PULLUDEN | PULLUP_EN}, + /* DCAN1 RX */ + {OFFSET(uart1_txd), MODE(2) | RXACTIVE}, + {-1}, +}; + +static struct module_pin_mux gpios[] = { + /* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */ + {OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS)}, + /* GPIO0_4 (SPI D1) - TA602 */ + {OFFSET(spi0_d1), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_5 (SPI CS0) - DISPLAY_ON_OFF */ + {OFFSET(spi0_cs0), (MODE(7) | PULLUDDIS)}, + /* GPIO0_7 (PWW0 OUT) - CAN TERM */ + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_19 (DMA_INTR0) - CLKOUT SYS */ + {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE)}, + /* GPIO0_20 (DMA_INTR1) - SPI1 nCS1 */ + {OFFSET(xdma_event_intr1), (MODE(7) | PULLUDEN | PULLUP_EN)}, + /* GPIO0_30 (GPMC_WAIT0) - TA601 */ + {OFFSET(gpmc_wait0), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO0_31 (GPMC_nWP) - SW601 PushButton */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO1_28 (GPMC_nWE) - FRAM_nWP */ + {OFFSET(gpmc_be1n), (MODE(7) | PULLUDDIS)}, + /* GPIO2_0 (GPMC_nCS3) - VBAT_OK */ + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) }, + /* GPIO2_2 (GPMC_nADV_ALE) - DCOK */ + {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | RXACTIVE)}, + /* GPIO2_4 (GPMC_nWE) - TST_BAST */ + {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS)}, + /* GPIO3_18 (MCASP0_ACLKR) - SW601 CNTup, mapped to Counter eQEB0A_in */ + {OFFSET(mcasp0_aclkr), (MODE(1) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_19 (MCASP0_FSR) - SW601 CNTdown, mapped to Counter eQEB0B_in */ + {OFFSET(mcasp0_fsr), (MODE(1) | PULLUDDIS | RXACTIVE)}, + /* GPIO3_20 (MCASP0_AXR1) - SW601 CNTdown, map to Counter eQEB0_index */ + {OFFSET(mcasp0_axr1), (MODE(1) | PULLUDDIS | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux uart0_pin_mux[] = { + /* UART0_CTS */ + {OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_RXD */ + {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, + /* UART0_TXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + /* I2C_DATA */ + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + /* I2C_SCLK */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux mii1_pin_mux[] = { + {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ + {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ + {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ + {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ + {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ + {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ + {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ + {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ + {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ + {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ + {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ + {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ + {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ + {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ + {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ + {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ + {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ + {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ + {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */ + {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */ + + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */ + + {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */ + {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */ + {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */ + {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */ + {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */ + {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */ + {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */ + {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */ + + {OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */ + {OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */ + {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */ + {OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */ + + {-1}, +}; +/* ------------------------ orig ----------------- */ +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); + configure_module_pin_mux(mii1_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(spi1_pin_mux); +#ifdef CONFIG_AM335X_USB1 + configure_module_pin_mux(usb1_pin_mux); +#endif + configure_module_pin_mux(dcan0_pin_mux); + configure_module_pin_mux(dcan1_pin_mux); +#ifdef CONFIG_MMC + configure_module_pin_mux(mmc1_pin_mux); +#endif + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(gpios); +} diff --git a/board/BuR/bur_kwb/u-boot.lds b/board/BuR/bur_kwb/u-boot.lds new file mode 100644 index 0000000..021f869 --- /dev/null +++ b/board/BuR/bur_kwb/u-boot.lds @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + board/BuR/bur_kwb/built-in.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + + /* + * Deprecated: this MMU section is used by pxa at present but + * should not be used by new boards/CPUs. + */ + . = ALIGN(4096); + .mmutable : { + *(.mmutable) + } + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/boards.cfg b/boards.cfg index 2dfd2b4..45e83ef 100644 --- a/boards.cfg +++ b/boards.cfg @@ -255,6 +255,7 @@ Active arm armv7 am33xx phytec pcm051 Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier r.meier@siemens.com Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier r.meier@siemens.com Active arm armv7 am33xx siemens rut rut - Roger Meier r.meier@siemens.com +Active arm armv7 am33xx BuR bur_kwb bur_kwb bur_kwb:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier hannes.petermaier@br-automation.com Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini trini@ti.com Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini trini@ti.com Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini trini@ti.com diff --git a/include/configs/bur_kwb.h b/include/configs/bur_kwb.h new file mode 100644 index 0000000..66048dd --- /dev/null +++ b/include/configs/bur_kwb.h @@ -0,0 +1,352 @@ +/* + * bur_kwb.h + * + * Copyright (C) 2013 Hannes Petermaier oe5hpm@oevsv.at + * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Author(s) + * ========= + * Petermaier Hannes (hpm) hannes.petermaier@br-automation.com + * + * History: + * ======== + * + * 30.01.2014 hpm ported from v2007 to v2014.01 + * + */ +#ifndef __CONFIG_BUR_KWB_H +#define __CONFIG_BUR_KWB_H +#define CONFIG_AM33XX +#include <config.h> +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +/* -------------------------------------------------------------------------*/ +/* -- undefinig unused features -- */ +/* prior defined from config_defaults.h */ +#undef CONFIG_BOOTM_LINUX +#undef CONFIG_BOOTM_NETBSD +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS +#undef CONFIG_GZIP +#undef CONFIG_ZLIB +/* prior defined from config_cmd_defaults.h */ +#undef CONFIG_CMD_CRC32 +/* prior defined from config_cmd_default.h */ +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG +/* -------------------------------------------------------------------------*/ +/* -- user-defines -- */ +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_SOURCE +#if _HPMTEST +#define CONFIG_SILENT_CONSOLE +#define CONFIG_SILENT_U_BOOT_ONLY +#define CONFIG_SILENT_CONSOLE_UPDATE_ON_SET +#define CONFIG_SYS_DEVICE_NULLDEV +#endif /* _HPMTEST */ +#define CONFIG_SYS_POSTCODE + +#define CONFIG_SYS_SCREEN +#define CONFIG_SYS_FBSIZE (480*272*4+32) +/* -------------------------------------------------------------------------*/ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20)/* 1GB */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ + +#include <asm/arch/omap.h> + +/* Network defines. */ +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ +#define CONFIG_CMD_DHCP +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 4 +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ + +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x402F0400 and 0x4030B800 as a download area and + * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also + * supports X-MODEM loading via UART, and we leverage this and then use + * Y-MODEM to load u-boot.img, when booted over UART. + */ +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif /* CONFIG_SPL_BUILD */ +/* -------------------------------------------------------------------------*/ +/* Common define for many platforms. */ +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON + +#define CONFIG_SYS_NO_FLASH + +/* Support both device trees and ATAGs. */ +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Our DDR memory always starts at 0x80000000 and U-Boot shall have + * relocated itself to higher in memory by the time this value is used. + */ +#define CONFIG_SYS_LOAD_ADDR 0x80000000 + +/* TODO: für release auf 0 setzen, damits gleich bootet */ +#define CONFIG_BOOTDELAY 1 + +/* -------------------------------------------------------------------------*/ +/* + * DDR information. We say (for simplicity) that we have 1 bank, + * always, even when we have more. We always start at 0x80000000, + * and we place the initial stack pointer in our SRAM. + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) +/* -------------------------------------------------------------------------*/ +/* Timer information. */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +/* -------------------------------------------------------------------------*/ +/* I2C IP block */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP24XX +#define CONFIG_CMD_I2C +/* -------------------------------------------------------------------------*/ +/* MMC/SD IP block */ +#if defined(CONFIG_EMMC_BOOT) + #define CONFIG_MMC + #define CONFIG_GENERIC_MMC + #define CONFIG_OMAP_HSMMC + #define CONFIG_CMD_MMC + #define CONFIG_SUPPORT_EMMC_BOOT + #define HAVE_BLOCK_DEVICE +#endif /* CONFIG_EMMC_BOOT */ + +/* GPIO block */ +#define CONFIG_OMAP_GPIO +#define CONFIG_CMD_GPIO + +/* -------------------------------------------------------------------------*/ +/* + * The following are general good-enough settings for U-Boot. We set a + * large malloc pool as we generally have a lot of DDR, and we opt for + * function over binary size in the main portion of U-Boot as this is + * generally easily constrained later if needed. We enable the config + * options that give us information in the environment about what board + * we are on so we do not need to rely on the command prompt. We set a + * console baudrate of 115200 and use the default baud rate table. + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_SYS_FBSIZE + \ + (32 * 1024)) +#define CONFIG_SYS_HUSH_PARSER +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# " +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */ +#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ + +/* As stated above, the following choices are optional. */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE + +/* -------------------------------------------------------------------------*/ +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ECHO +/* + * Common filesystems support. When we have removable storage we + * enabled a number of useful commands and support. + */ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE) +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_FS_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_FS_GENERIC +#endif /* CONFIG_MMC */ + +/* + * Our platforms make use of SPL to initalize the hardware (primarily + * memory) enough for full U-Boot to be loaded. We also support Falcon + * Mode so that the Linux kernel can be booted directly from SPL + * instead, if desired. We make use of the general SPL framework found + * under common/spl/. Given our generally common memory map, we set a + * number of related defaults and sizes here. + */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#undef CONFIG_SPL_OS_BOOT +/* -------------------------------------------------------------------------*/ +/* + * Place the image at the start of the ROM defined image space. + * We limit our size to the ROM-defined downloaded image area, and use the + * rest of the space for stack. We load U-Boot itself into memory at + * 0x80800000 for legacy reasons (to not conflict with older SPLs). We + * have our BSS be placed 1MiB after this, to allow for the default + * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. + * We have the SPL malloc pool at the end of the BSS area. + */ +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#undef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SPL_BSS_START_ADDR 0x80A00000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN +/* -------------------------------------------------------------------------*/ +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ + +#ifdef CONFIG_MMC +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#endif /* CONFIG_MMC */ + +/* General parts of the framework, required. */ +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +/* -------------------------------------------------------------------------*/ +#define MACH_TYPE_TIAM335EVM 3589/* Until the next sync */ +#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* Custom script for NOR */ +#define CONFIG_SYS_LDSCRIPT "board/BuR/bur_kwb/u-boot.lds" +/* -------------------------------------------------------------------------*/ +/* Always 128 KiB env size */ +#define CONFIG_ENV_SIZE (128 << 10) + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=0\0" \ + "loadaddr=0x80100000\0" \ + "bootfile=arimg\0" \ + "netboot=echo Booting from network ...; " \ + "setenv autoload 0; " \ + "dhcp; " \ + "setenv bootfile arimg; " \ + "tftp ${loadaddr} ${bootfile}; " \ + "mw 0x80001100 0 1; " \ + "go ${loadaddr}\0" \ + "usbupdate=echo Updating UBOOT from USB-Stick ...; " \ + "usb start; " \ + "fatload usb 0 0x80000000 updateubootusb.img; " \ + "source;\0" \ + "netupdate=echo Updating UBOOT from Network (TFTP) ...; " \ + "setenv autoload 0; " \ + "dhcp;" \ + "tftp 0x80000000 updateUBOOT.img;" \ + "source;\0" +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_BOOTCOMMAND \ + "run usbupdate;" +/* -------------------------------------------------------------------------*/ +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK 48000000 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ +#define CONFIG_BAUDRATE 115200 + +/* PMIC support */ +#define CONFIG_POWER_TPS65217 + +/* SPL */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +/* -------------------------------------------------------------------------*/ +/* CPSW support */ +#define CONFIG_SPL_ETH_SUPPORT +/* General network SPL, both CPSW and USB gadget RNDIS */ +#define CONFIG_SPL_NET_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" +/* -------------------------------------------------------------------------*/ +/* USB configuration. */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_MUSB_HOST +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_HOST + +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif /* CONFIG_MUSB_HOST */ +/* -------------------------------------------------------------------------*/ +#if defined(CONFIG_EMMC_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#endif /* CONFIG_EMMC_BOOT */ + +/* Network. */ +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_NATSEMI + +#endif /* __CONFIG_BUR_KWB_H */