
12 Jul
2024
12 Jul
'24
7:14 p.m.
Right now, the maximal transfer speed from an SPI flash on a V3s is about 240kb/s. That is pretty slow. It turns out, that due to an error u-boot is setting the maximum frequency to 1MHz. By fixing that another bug is unearthed: one cannot set a clock divider of 1:1 due to the handling between CDR1 and CDR2 handling. By fixing that I achieved loading speeds of about 1.5MB/s.
Michael Walle (2): spi: sunxi: drop max_hz handling spi: sunxi: fix clock divider calculation for max frequency setting
drivers/spi/spi-sunxi.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-)
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2.39.2