Hi,
On 29 July 2015 at 14:13, Tom Warren twarren@nvidia.com wrote:
Added PLL variables (dividers mask/shift, lock enable/detect, etc.) to new pllinfo struct for each Soc/PLL. PLLA/C/D/E/M/P/U/X.
Used pllinfo struct in all clock functions, validated on T210. Should be equivalent to prior code on T124/114/30/20 but needs test.
Corrections to divm mask vs shift and T20/30 divN masks thanks to Marcel Ziswiler.
Signed-off-by: Tom Warren twarren@nvidia.com
arch/arm/include/asm/arch-tegra/clk_rst.h | 32 +------ arch/arm/include/asm/arch-tegra/clock.h | 21 +++++ arch/arm/include/asm/arch-tegra210/clock-tables.h | 1 + arch/arm/mach-tegra/clock.c | 108 ++++++++-------------- arch/arm/mach-tegra/cpu.c | 18 ++-- arch/arm/mach-tegra/tegra114/clock.c | 57 +++++++++--- arch/arm/mach-tegra/tegra114/cpu.c | 39 +++----- arch/arm/mach-tegra/tegra124/clock.c | 44 ++++++++- arch/arm/mach-tegra/tegra124/cpu.c | 31 +++---- arch/arm/mach-tegra/tegra20/clock.c | 32 +++++++ arch/arm/mach-tegra/tegra210/clock.c | 31 ++++++- arch/arm/mach-tegra/tegra30/clock.c | 45 ++++++--- 12 files changed, 285 insertions(+), 174 deletions(-)
This breaks the display on Nyan.
I think I found two problems - I'll send out a patch.
Regards, Simon