Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices.
Signed-off-by: York Sun yorksun@freescale.com --- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 14 +++++++++++++- arch/powerpc/cpu/mpc8xxx/ddr/options.c | 3 ++- arch/powerpc/include/asm/fsl_ddr_sdram.h | 3 +++ 3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 2b43e73..db7cf11 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -174,7 +174,19 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo, switch (pinfo->memctl_opts[i].data_bus_width) { case 2: /* 16-bit */ - printf("can't handle 16-bit mode yet\n"); + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + unsigned int dw; + if (!pinfo->dimm_params[i][j].n_ranks) + continue; + dw = pinfo->dimm_params[i][j].primary_sdram_width; + if ((dw == 72 || dw == 64)) { + dbw_cap_adj[i] = 2; + break; + } else if ((dw == 40 || dw == 32)) { + dbw_cap_adj[i] = 1; + break; + } + } break;
case 1: diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 80c7046..02efe58 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -438,7 +438,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, popts->OTF_burst_chop_en = 0; /* on-the-fly burst chop disable */ popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */ #else - if (popts->data_bus_width == 1) { /* 32-bit bus */ + if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) { + /* 32-bit or 16-bit bus */ popts->OTF_burst_chop_en = 0; popts->burst_length = DDR_BL8; } else { diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 127a840..1778cc5 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -181,6 +181,9 @@ typedef struct memctl_options_partial_s { unsigned int all_DIMMs_minimum_tRCD_ps; } memctl_options_partial_t;
+#define DDR_DATA_BUS_WIDTH_64 0 +#define DDR_DATA_BUS_WIDTH_32 1 +#define DDR_DATA_BUS_WIDTH_16 2 /* * Generalized parameters for memory controller configuration, * might be a little specific to the FSL memory controller