H/W used for test: TI Blaze/Tablet OMAP4470 Processor Board (750-2173-005) mounted on a custom main board (MMS benvolio4).
Fixed bug in vcores_data omap4460_volts struct referencing tps62361 instead of twl6030 for core and mm voltages.
Fixed some comments.
Signed-off-by: Lubomir Popov lpopov@mm-sol.com
--- arch/arm/cpu/armv7/omap4/hw_data.c | 53 ++++++++++++++++++++++-- arch/arm/cpu/armv7/omap4/hwinit.c | 6 +++ arch/arm/cpu/armv7/omap4/sdram_elpida.c | 65 ++++++++++++++++++++++++++---- arch/arm/include/asm/arch-omap4/clocks.h | 7 +++- arch/arm/include/asm/arch-omap4/omap.h | 1 + 5 files changed, 119 insertions(+), 13 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 7551b98..fc4990a 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -7,6 +7,9 @@ * * Sricharan R r.sricharan@ti.com * + * 03/2013 Lubomir Popov lpopov@mm-sol.com l-popov@ti.com + * Added basic support for 750-2173 OMAP4470 board. + * * See file CREDITS for list of people who contributed to this * project. * @@ -66,6 +69,7 @@ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { /* * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) * OMAP4430 OPP_TURBO frequency + * OMAP4470 OPP_NOM frequency */ static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ @@ -92,6 +96,7 @@ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { };
/* OMAP4460 OPP_NOM frequency */ +/* OMAP4470 OPP_NOM (Low Power) frequency */ static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ @@ -214,16 +219,30 @@ struct dplls omap4460_dplls = { .ddr = NULL };
+struct dplls omap4470_dplls = { + .mpu = mpu_dpll_params_1600mhz, + .core = core_dpll_params_1600mhz, + .per = per_dpll_params_1536mhz, + .iva = iva_dpll_params_1862mhz, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz, + .ddr = NULL +}; + struct pmic_data twl6030_4430es1 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, - .step = 12660, /* 10 mV represented in uV */ + .step = 12660, /* 12.7 mV represented in uV */ /* The code starts at 1 not 0 */ .start_code = 1, };
struct pmic_data twl6030 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, - .step = 12660, /* 10 mV represented in uV */ + .step = 12660, /* 12.7 mV represented in uV */ /* The code starts at 1 not 0 */ .start_code = 1, }; @@ -236,6 +255,13 @@ struct pmic_data tps62361 = { .gpio_en = 1 };
+struct pmic_data twl6032 = { + .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, + .step = 12660, /* 12.7 mV represented in uV */ + /* The code starts at 1 not 0 */ + .start_code = 1, +}; + struct vcores_data omap4430_volts_es1 = { .mpu.value = 1325, .mpu.addr = SMPS_REG_ADDR_VCORE1, @@ -271,11 +297,25 @@ struct vcores_data omap4460_volts = {
.core.value = 1200, .core.addr = SMPS_REG_ADDR_VCORE1, - .core.pmic = &tps62361, + .core.pmic = &twl6030,
.mm.value = 1200, .mm.addr = SMPS_REG_ADDR_VCORE2, - .mm.pmic = &tps62361, + .mm.pmic = &twl6030, +}; + +struct vcores_data omap4470_volts = { + .mpu.value = 1203, + .mpu.addr = SMPS1_REG_ADDR_MPU, + .mpu.pmic = &twl6032, + + .core.value = 1127, + .core.addr = SMPS2_REG_ADDR_CORE, + .core.pmic = &twl6032, + + .mm.value = 1139, + .mm.addr = SMPS5_REG_ADDR_MM, + .mm.pmic = &twl6032, };
/* @@ -483,6 +523,11 @@ void hw_data_init(void) *omap_vcores = &omap4460_volts; break;
+ case OMAP4470_ES1_0: + *dplls_data = &omap4470_dplls; + *omap_vcores = &omap4470_volts; + break; + default: printf("\n INVALID OMAP REVISION "); } diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 2db517b..586ffe2 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -9,6 +9,9 @@ * Aneesh V aneesh@ti.com * Steve Sakoman steve@sakoman.com * + * 03/2013 Lubomir Popov lpopov@mm-sol.com l-popov@ti.com + * Added basic support for 750-2173 OMAP4470 board. + * * See file CREDITS for list of people who contributed to this * project. * @@ -153,6 +156,9 @@ void init_omap_revision(void) break; case MIDR_CORTEX_A9_R2P10: switch (readl(CONTROL_ID_CODE)) { + case OMAP4470_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP4470_ES1_0; + break; case OMAP4460_CONTROL_ID_CODE_ES1_1: *omap_si_rev = OMAP4460_ES1_1; break; diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index 20fc552..61dadc8 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -7,6 +7,9 @@ * * Aneesh V aneesh@ti.com * + * 03/2013 Lubomir Popov lpopov@mm-sol.com l-popov@ti.com + * Added basic support for 750-2173 OMAP4470 board. + * * See file CREDITS for list of people who contributed to this * project. * @@ -90,6 +93,21 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = { .emif_ddr_phy_ctlr_1 = 0x049ff418 };
+/* 4 Gb devices on the 750-2173 4470 Processor Board */ +const struct emif_regs emif_regs_elpida_400_mhz_1cs = { + .sdram_config_init = 0x80800eb2, + .sdram_config = 0x80801ab2, + .ref_ctrl = 0x00000618, + .sdram_tim1 = 0x10eb0662, + .sdram_tim2 = 0x20370dd2, + .sdram_tim3 = 0x00b1c33f, + .read_idle_ctrl = 0x000501ff, + .zq_config = 0xd00b3215, + .temp_alert_config = 0x58016893, + .emif_ddr_phy_ctlr_1_init = 0x449ffff5, + .emif_ddr_phy_ctlr_1 = 0x449ff408 +}; + const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, .dmm_lisa_map_1 = 0, @@ -114,6 +132,22 @@ const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = { .is_ma_present = 0x1 };
+const struct dmm_lisa_map_regs lisa_map_4G_x_1_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x0 +}; + +const struct dmm_lisa_map_regs ma_lisa_map_4G_x_1_x_2 = { + .dmm_lisa_map_0 = 0xFF020100, + .dmm_lisa_map_1 = 0, + .dmm_lisa_map_2 = 0, + .dmm_lisa_map_3 = 0x80640300, + .is_ma_present = 0x1 +}; + static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { u32 omap4_rev = omap_revision(); @@ -123,8 +157,10 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) *regs = &emif_regs_elpida_380_mhz_1cs; else if (omap4_rev == OMAP4430_ES2_0) *regs = &emif_regs_elpida_200_mhz_2cs; - else + else if (omap4_rev < OMAP4470_ES1_0) *regs = &emif_regs_elpida_400_mhz_2cs; + else + *regs = &emif_regs_elpida_400_mhz_1cs; } void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); @@ -138,8 +174,10 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs *dmm_lisa_regs = &lisa_map_2G_x_1_x_2; else if (omap_rev < OMAP4460_ES1_0) *dmm_lisa_regs = &lisa_map_2G_x_2_x_2; - else + else if (omap_rev < OMAP4470_ES1_0) *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2; + else + *dmm_lisa_regs = &ma_lisa_map_4G_x_1_x_2; }
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs) @@ -154,20 +192,31 @@ static const struct lpddr2_device_details elpida_2G_S4_details = { .manufacturer = LPDDR2_MANUFACTURER_ELPIDA };
+static const struct lpddr2_device_details elpida_4G_S4_details = { + .type = LPDDR2_TYPE_S4, + .density = LPDDR2_DENSITY_4Gb, + .io_width = LPDDR2_IO_WIDTH_32, + .manufacturer = LPDDR2_MANUFACTURER_ELPIDA +}; + struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs, struct lpddr2_device_details *lpddr2_dev_details) { u32 omap_rev = omap_revision();
/* EMIF1 & EMIF2 have identical configuration */ - if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) { - /* Nothing connected on CS1 for ES1.0 */ + if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) + && (cs == CS1)) { + /* Nothing connected on CS1 for 4430/4470 ES1.0 */ return NULL; - } else { - /* In all other cases Elpida 2G device */ + } else if (omap_rev < OMAP4470_ES1_0) { + /* In all other 4430/4460 cases Elpida 2G device */ *lpddr2_dev_details = elpida_2G_S4_details; - return lpddr2_dev_details; + } else { + /* 4470: 4G device */ + *lpddr2_dev_details = elpida_4G_S4_details; } + return lpddr2_dev_details; }
struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, @@ -281,7 +330,7 @@ void emif_get_device_timings_sdp(u32 emif_nr, /* Identical devices on EMIF1 & EMIF2 */ *cs0_device_timings = &elpida_2G_S4_timings;
- if (omap_rev == OMAP4430_ES1_0) + if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0)) *cs1_device_timings = NULL; else *cs1_device_timings = &elpida_2G_S4_timings; diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index ed7a1c8..1b89158 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -188,11 +188,16 @@ /* PRM_VC_VAL_BYPASS */ #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
-/* SMPS */ +/* PMIC Slave Address */ #define SMPS_I2C_SLAVE_ADDR 0x12 +/* TWL6030 SMPS */ #define SMPS_REG_ADDR_VCORE1 0x55 #define SMPS_REG_ADDR_VCORE2 0x5B #define SMPS_REG_ADDR_VCORE3 0x61 +/* TWL6032 SMPS */ +#define SMPS1_REG_ADDR_MPU 0x55 /* mpu */ +#define SMPS5_REG_ADDR_MM 0x49 /* mm */ +#define SMPS2_REG_ADDR_CORE 0x5B /* core */
#define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 5f321fe..e3362c8 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -65,6 +65,7 @@ #define OMAP4_CONTROL_ID_CODE_ES2_3 0x6B95C02F #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F +#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F
/* UART */ #define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)