/*
 * This code is based on the code for the memory setup for the
 * lubbock platform. Modified and removed the code to meet the
 * needs of the bolfenk platform.
 *
 * Modified by Matej Kupljen <matej.kupljen@ultra.si>
 * Copyright (C) 2004, Ultra d.o.o.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>


/*
 * 	Memory setup
 */


.globl memsetup
memsetup:

	mov      r10, lr

	/* Set up GPIO pins first ----------------------------------------- */

	ldr	r0, =GPSR0
	ldr	r1, =BOLFENK_GPSR0_VAL
	str	r1, [r0]

	ldr	r0, =GPSR1
	ldr	r1, =BOLFENK_GPSR1_VAL
	str	r1, [r0]

	ldr	r0, =GPSR2
	ldr	r1, =BOLFENK_GPSR2_VAL
	str	r1, [r0]

	ldr	r0, =GPCR0
	ldr	r1, =BOLFENK_GPCR0_VAL
	str	r1, [r0]

	ldr	r0, =GPCR1
	ldr	r1, =BOLFENK_GPCR1_VAL
	str	r1, [r0]

	ldr	r0, =GPCR2
	ldr	r1, =BOLFENK_GPCR2_VAL
	str	r1, [r0]

	ldr	r0, =GPDR0
	ldr	r1, =BOLFENK_GPDR0_VAL
	str	r1, [r0]

	ldr	r0, =GPDR1
	ldr	r1, =BOLFENK_GPDR1_VAL
	str	r1, [r0]

	ldr	r0, =GPDR2
	ldr	r1, =BOLFENK_GPDR2_VAL
	str	r1, [r0]

	ldr	r0, =GAFR0_L
	ldr	r1, =BOLFENK_GAFR0_L_VAL
	str	r1, [r0]

	ldr	r0, =GAFR0_U
	ldr	r1, =BOLFENK_GAFR0_U_VAL
	str	r1, [r0]

	ldr	r0, =GAFR1_L
	ldr	r1, =BOLFENK_GAFR1_L_VAL
	str	r1, [r0]

	ldr	r0, =GAFR1_U
	ldr	r1, =BOLFENK_GAFR1_U_VAL
	str	r1, [r0]

	ldr	r0, =GAFR2_L
	ldr	r1, =BOLFENK_GAFR2_L_VAL
	str	r1, [r0]

	ldr	r0, =GAFR2_U
	ldr	r1, =BOLFENK_GAFR2_U_VAL
	str	r1, [r0]

	ldr	r0, =PSSR				/* enable GPIO pins */
	ldr	r1, =BOLFENK_PSSR_VAL
	str	r1, [r0]

	/* ---------------------------------------------------------------- */
	/* Enable memory interface                                          */
	/*                                                                  */
	/* The sequence below is based on the recommended init steps        */
	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	/* Chapter 10.                                                      */
	/* ---------------------------------------------------------------- */

	/* ---------------------------------------------------------------- */
	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
	/*         clocks to settle. Only necessary after hard reset...     */
	/*         FIXME: can be optimized later                            */
	/* ---------------------------------------------------------------- */

	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
	mov	r2, #0
	str	r2, [r3]
	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
					/* so 0x300 should be plenty        */
1:
	ldr	r2, [r3]
	cmp	r4, r2
	bgt	1b

mem_init:

	ldr r1, =MEMC_BASE		/* get memory controller base addr. */

	/* ---------------------------------------------------------------- */
	/* Step 2a: Initialize Asynchronous static memory controller        */
	/* ---------------------------------------------------------------- */

	/* MSC registers: timing, bus width, mem type                       */

	/* MSC0: nCS(0,1)                                                   */
	ldr 	r2, =BOLFENK_MSC0_VALUE
	str	r2, [r1, #MSC0_OFFSET]
	ldr	r2, [r1, #MSC0_OFFSET]		/* read back to ensure      */
						/* that data latches        */
	/* MSC1: nCS(2,3)                                                   */
	ldr	r2, =BOLFENK_MSC1_VALUE
	str	r2, [r1, #MSC1_OFFSET]
	ldr	r2, [r1, #MSC1_OFFSET]

	/* MSC2: nCS(4,5)                                                   */
	ldr	r2,  =BOLFENK_MSC2_VALUE
	str	r2,  [r1, #MSC2_OFFSET]
	ldr	r2,  [r1, #MSC2_OFFSET]

	/*
	 * NOTE:
	 * On the bolfenk platform two types of RAMs are used, one is for
	 * 32 MBytes, the second one is for the 64 MBytes. The size of the
	 * RAM can be configured in the bolfenk.h file. It can also be
	 * configured, so that the size of the RAM is determined by reading
	 * the LSB bit of the DIP switch on the bolfenk platform.
	 * We store the:
	 *   - MDREFR value into the reg r5
	 *   - MDCNFG value into the reg r6
	 */

	/*
	 * NOTE 1:
	 * Execute NOP if we have 64 MB of memory, otherwise the board
	 * DOES NOT RESUME FROM SLEEP!!
	 * If we have 32 MB of memory, we must not execute NOP!!!
	 */

	/* nop */

#if defined ( BOLFENK_SDRAM_MT48LC8M16A2 )
	ldr	r5, =BOLFENK_MDREFR_VALUE_32M
	ldr	r6, =BOLFENK_MDCNFG_VALUE_32M
#elif defined ( BOLFENK_SDRAM_MT48LC16M16A2 )
	ldr	r5, =BOLFENK_MDREFR_VALUE_64M
	ldr	r6, =BOLFENK_MDCNFG_VALUE_64M
#elif defined ( BOLFENK_SDRAM_SELECT_FROM_DIP )
	ldr	r4, =BOLFENK_DIP_SWITCH_ADDRESS
	ldr	r5, [r4]
	and	r5, r5, #0x00010000
	cmp	r5, #0x0
	ldrne	r5, =BOLFENK_MDREFR_VALUE_32M
	ldrne	r6, =BOLFENK_MDCNFG_VALUE_32M
	ldreq	r5, =BOLFENK_MDREFR_VALUE_64M
	ldreq	r6, =BOLFENK_MDCNFG_VALUE_64M
#else
#error SDRAM chip not defined
#endif

	/* ---------------------------------------------------------------- */
	/* Step 2b: Initialize Card Interface                               */
	/* ---------------------------------------------------------------- */

	/*
	 * Note:
	 * Not needed (yet) on a Bolfenk platorm
	 */

	/* ---------------------------------------------------------------- */
	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
	/* ---------------------------------------------------------------- */


	/* ---------------------------------------------------------------- */
	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
	/* ---------------------------------------------------------------- */

	/* Before accessing MDREFR we need a valid DRI field, so we set     */
	/* this to power on defaults + DRI field.                           */

	mov	r3, r5
	ldr	r2, =0xFFF
	and	r3, r3, r2
	/*ldr	r4, =0x03ca4000*/
	ldr	r4, =(MDREFR_K0RUN | MDREFR_E0PIN | MDREFR_SLFRSH)
	orr	r4, r4, r3
	str	r4, [r1, #MDREFR_OFFSET]	/* write back MDREFR        */
	ldr	r4, [r1, #MDREFR_OFFSET]

	/* Note: preserve the mdrefr value in r4                            */


	/* ---------------------------------------------------------------- */
	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	/* ---------------------------------------------------------------- */

	/* Initialize SXCNFG register. Assert the enable bits               */

	/* Write SXMRS to cause an MRS command to all enabled banks of      */
	/* synchronous static memory. Note that SXLCR need not be written   */
	/* at this time.                                                    */

	/* FIXME: we use async mode for now                                 */


	/* ---------------------------------------------------------------- */
	/* Step 4: Initialize SDRAM                                         */
	/* ---------------------------------------------------------------- */

	/* set MDREFR according to user define with exception of a few bits */

	/* SDRAM controller should go trough the following stages	    */
	/* self-refresh and clock-stop -> self-refresh 			    */

	orr	r4, r4, #(MDREFR_K1RUN)
	orr	r4, r4, #(MDREFR_K2RUN)

	/* Configure K1DB2 and K2DB2					    */
	/* NOTE: r5 is not used below this line any more!!		    */
	and	r5, r5, #(MDREFR_K1DB2 | MDREFR_K2DB2)
	orr	r4, r4, r5

	/* self-refresh -> power-down 					    */
	bic	r4, r4, #(MDREFR_SLFRSH)

	/* power-down -> PWRDNX 					    */
	orr	r4, r4, #(MDREFR_E1PIN)
	str	r4, [r1, #MDREFR_OFFSET]    /* write back MDREFR            */
	ldr	r4, [r1, #MDREFR_OFFSET]


	/* Configure MDCNFG, but do not enable the SDRAM partitions	    */
	mov	r4, r6
	bic	r4, r4, #(MDCNFG_DE0 | MDCNFG_DE1)

	str	r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */


	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
	/*          100..200 �sec.                                          */

	ldr	r3, =OSCR		/* reset the OS Timer Count to zero */
	mov	r2, #0
	str	r2, [r3]
	ldr	r4, =0x300		/* really 0x2E1 is about 200usec,   */
					/* so 0x300 should be plenty        */
2:
	ldr	r2, [r3]
	cmp	r4, r2
	bgt	2b


	/* Step 4f: Trigger a number (usually 8) refresh cycles by          */
	/*          attempting non-burst read or write accesses to disabled */
	/*          SDRAM, as commonly specified in the power up sequence   */
	/*          documented in SDRAM data sheets. The address(es) used   */
	/*          for this purpose must not be cacheable.                 */

	ldr	r3, =CFG_DRAM_BASE
	ldr	r2, [r3]
	ldr	r2, [r3]
	ldr	r2, [r3]
	ldr	r2, [r3]
	ldr	r2, [r3]
	ldr	r2, [r3]
	ldr	r2, [r3]
	ldr	r2, [r3]


	/* Step 4g: Write MDCNFG with enable bits asserted                  */
	/*          (MDCNFG:DEx set to 1).                                  */
	/* NOTE: Modified!! Only enable SDRAM partition 0                   */

	ldr	r3, [r1, #MDCNFG_OFFSET]
	orr	r3, r3, #(MDCNFG_DE0)
	str	r3, [r1, #MDCNFG_OFFSET]
	ldr	r3, [r1, #MDCNFG_OFFSET]

	/* Step 4h: Write MDMRS.                                            */

	ldr	r2, =BOLFENK_MDMRS_VAL
	str	r2, [r1, #MDMRS_OFFSET]

	/* We are finished with Intel's memory controller initialisation    */

	/*
	 * Now check if we were in the sleep mode.
	 */

	/* check if we return from Sleep Mode via RCSR 			    */
	ldr	r0, =RCSR
	ldr	r1, [r0]

	/* mask RCSR_HWR|RCSR_WDR|RCSR_AMR|RCSR_GPR 			    */
	and	r1, r1, #0x0f

	/* clear Reset Control State 					    */
	str	r1, [r0]

	/* RCSR_SMR(sleep mode) 					    */
	teq	r1, #0x04
	beq	WakeUp

endmemsetup:
	mov	pc, lr

WakeUp:
	/* Read the value of the Power Manager Scratch Pad Register 
	 * and jump to it 
	 */
	ldr	r0, =PSPR
	ldr	r1, [r0]
	mov	pc, r1
