Hi Michal
We are doing some work on an MPSoC UZ3EG platform part of which requires us to replace FSBL with SPL.
It seems the actual boot process is becoming an issue on these SoCs; currently, 1) we embed the PMU firmware on SPL so the bootrom can extract it and program it; 2) then SPL configures the PMU using a platform specific binary that gets built also with SPL; and finally, 3) SPL sets up the DDR using its psu_init_gpl.c settings (also board specific, part of the XSA).
It is this final step in the boot sequence that is being broken by the Dynamic DDR DIMM configuration feature [1]
[1] https://www.xilinx.com/support/answers/75768.html
Are you aware of any work in progress to support this? Any thoughts on how to work around it and train the DDR? will the functionality required to implmenet Dynamic DDR DIMM configuration be added as a separate file to the XSA tarball or will we need to do some native implementation in SPL?
Becase without a change in the last link in the process chain described earlier (calls to psu_init()), DDR just wont be accessible to U-BOOT or OP-TEE.
In our case, we were able to boot from QSPI, boot SPL (in OCM), have SPL unpack and validate the FIT image, execute TF-A(in OCM), but then any jumps to OP-TEE or U-BOOT would obviously not progress since the DDR wasnt properly trained/initialized.
so, any thoughts or plans you can share?
TIA!
jorge