This driver manages the SPI controller present on this SoC.
Signed-off-by: Álvaro Fernández Rojas noltari@gmail.com Reviewed-by: Daniel Schwierzeck daniel.schwierzeck@gmail.com Reviewed-by: Jagan Teki jagan@openedev.com Reviewed-by: Simon Glass sjg@chromium.org --- v9: no changes v8: no changes v7: no changes v6: no changes v5: no changes v4: no changes v3: no changes v2: add spi alias
arch/mips/dts/brcm,bcm6358.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 4f63cf80e0..1662783279 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -12,6 +12,10 @@ / { compatible = "brcm,bcm6358";
+ aliases { + spi0 = &spi; + }; + cpus { reg = <0xfffe0000 0x4>; #address-cells = <1>; @@ -142,6 +146,19 @@ status = "disabled"; };
+ spi: spi@fffe0800 { + compatible = "brcm,bcm6358-spi"; + reg = <0xfffe0800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6358_CLK_SPI>; + resets = <&periph_rst BCM6358_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <4>; + + status = "disabled"; + }; + memory-controller@fffe1200 { compatible = "brcm,bcm6358-mc"; reg = <0xfffe1200 0x4c>;