-----Original Message----- From: Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Sent: Wednesday, March 31, 2021 10:39 PM To: u-boot@lists.denx.de Cc: Marek Vasut marex@denx.de; Tan, Ley Foon ley.foon.tan@intel.com; See, Chin Liang chin.liang.see@intel.com; Simon Goldschmidt simon.k.r.goldschmidt@gmail.com; Chee, Tien Fong tien.fong.chee@intel.com; Westergreen, Dalon dalon.westergreen@intel.com; Simon Glass sjg@chromium.org; Gan, Yau Wai yau.wai.gan@intel.com; Lim, Elly Siew Chin elly.siew.chin.lim@intel.com Subject: [v1 06/17] drivers: clk: Add memory clock driver for Intel N5X device
Add memory clock manager driver for N5X. Provides memory clock initialization and enable functions.
Signed-off-by: Siew Chin Lim elly.siew.chin.lim@intel.com
drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-mem-n5x.c | 136 +++++++++++++++++++++++++++++++++++++++ drivers/clk/altera/clk-mem-n5x.h | 84 ++++++++++++++++++++++++ 3 files changed, 221 insertions(+) create mode 100644 drivers/clk/altera/clk-mem-n5x.c create mode 100644 drivers/clk/altera/clk-mem-n5x.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index 38cd730685..33db092918 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o +obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem- n5x.c new file mode 100644 index 0000000000..ca44998641 --- /dev/null +++ b/drivers/clk/altera/clk-mem-n5x.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2020-2021 Intel Corporation <www.intel.com> */
+#include <common.h> +#include <asm/arch/clock_manager.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include "clk-mem-n5x.h" +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/util.h> +#include <dt-bindings/clock/n5x-clock.h>
Sorting the include name.
+DECLARE_GLOBAL_DATA_PTR;
+struct socfpga_mem_clk_plat {
- void __iomem *regs;
+};
+++ b/drivers/clk/altera/clk-mem-n5x.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2020-2021 Intel Corporation <www.intel.com> */
+#ifndef _CLK_MEM_N5X_ +#define _CLK_MEM_N5X_
+#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif
+/* Clock Manager registers */ +#define MEMCLKMGR_STAT 4 +#define MEMCLKMGR_INTRGEN 8 +#define MEMCLKMGR_INTRMSK 0x0C
For consistency, use small letter for 0x0C.
+#define MEMCLKMGR_INTRCLR 0x10 +#define MEMCLKMGR_INTRSTS 0x14 +#define MEMCLKMGR_INTRSTK 0x18 +#define MEMCLKMGR_INTRRAW 0x1C
Same here.
+/* Memory Clock Manager PPL group registers */ +#define MEMCLKMGR_MEMPLL_EN 0x20 +#define MEMCLKMGR_MEMPLL_ENS 0x24 +#define MEMCLKMGR_MEMPLL_ENR 0x28 +#define MEMCLKMGR_MEMPLL_BYPASS 0x2c +#define MEMCLKMGR_MEMPLL_BYPASSS 0x30 +#define MEMCLKMGR_MEMPLL_BYPASSR 0x34 +#define MEMCLKMGR_MEMPLL_MEMDIV 0x38 +#define MEMCLKMGR_MEMPLL_PLLGLOB 0x3c +#define MEMCLKMGR_MEMPLL_PLLCTRL 0x40 +#define MEMCLKMGR_MEMPLL_PLLDIV 0x44 +#define MEMCLKMGR_MEMPLL_PLLOUTDIV 0x48 +#define MEMCLKMGR_MEMPLL_EXTCNTRST 0x4c
+#define MEMCLKMGR_CTRL_BOOTMODE BIT(0)
+#define MEMCLKMGR_STAT_MEMPLL_LOCKED BIT(8)
+#define MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK \
- (MEMCLKMGR_STAT_MEMPLL_LOCKED)
+#define MEMCLKMGR_INTER_MEMPLLLOCKED_MASK 0x00000001 +#define MEMCLKMGR_INTER_MEMPLLLOST_MASK 0x00000004
+#define MEMCLKMGR_BYPASS_MEMPLL_ALL 0x1
+#define MEMCLKMGR_MEMDIV_MPFEDIV_OFFSET 0 +#define MEMCLKMGR_MEMDIV_APBDIV_OFFSET 4 +#define MEMCLKMGR_MEMDIV_DFICTRLDIV_OFFSET 8 +#define MEMCLKMGR_MEMDIV_DFIDIV_OFFSET 12 +#define MEMCLKMGR_MEMDIV_DFICTRLDIV_MASK 0x1 +#define MEMCLKMGR_MEMDIV_DIVIDER_MASK 0x3
+#define MEMCLKMGR_PLLGLOB_PSRC_MASK GENMASK(17, 16) +#define MEMCLKMGR_PLLGLOB_PSRC_OFFSET 16 +#define MEMCLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK BIT(28) +#define MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
+#define MEMCLKMGR_PSRC_EOSC1 0 +#define MEMCLKMGR_PSRC_INTOSC 1 +#define MEMCLKMGR_PSRC_F2S 2
+#define MEMCLKMGR_PLLCTRL_BYPASS_MASK BIT(0) +#define MEMCLKMGR_PLLCTRL_RST_N_MASK BIT(1)
+#define MEMCLKMGR_PLLDIV_DIVR_MASK GENMASK(5, 0) +#define MEMCLKMGR_PLLDIV_DIVF_MASK GENMASK(16, 8) +#define MEMCLKMGR_PLLDIV_DIVQ_MASK GENMASK(26, 24) +#define MEMCLKMGR_PLLDIV_RANGE_MASK GENMASK(30, 28)
+#define MEMCLKMGR_PLLDIV_DIVR_OFFSET 0 +#define MEMCLKMGR_PLLDIV_DIVF_OFFSET 8 +#define MEMCLKMGR_PLLDIV_DIVQ_QDIV_OFFSET 24 +#define MEMCLKMGR_PLLDIV_RANGE_OFFSET 28
+#define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) +#define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0
+#define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7) +#define MEMCLKMGR_EXTCNTRST_ALLCNTRST \
- (MEMCLKMGR_EXTCNTRST_C0CNTRST)
+#endif /* _CLK_MEM_N5X_ */
2.13.0