In message 1BF8A0AAE2F4B94A9D7B247FE51D511403EC16@CHM-EMAIL1.ad.mc.com you wrote:
I have a question regarding porting U-Boot to a Xilinx Virtex-II Pro. I think I understand most of the porting requirements and have modified the Xilinx ML300 board to suit my boards peripherals and memory. My problem is that when I download the u-boot ELF to my hardware (using JTAG debugger) it seems to lock up during or after the routine 'relocate_code'. The difference in my PPC405 sub-system and the ML300 is that my SDRAM is not mapped a 0x0. My memory is mapped at 0x80000000. I looked in the README file and found the define
I guess you can change this mapping, right? Change it.
CFG_SDRAM_BASE. I then located this define in the file ML300.h and changed it to 0x80000000. However, I also found the note * Please note that CFG_SDRAM_BASE _must_ start at 0 . My question is, is there some sort of dependence that u-boot (for the PPC 405) has on the memory residing at 0. The thing I ran into when porting VxWorks to this system
Yes, for all PowerPC.
is that the EVPR register (the Vector table pointer) of the 405 needs to be modified to allow for the memory to reside at an address other than 0. Is there any know issue with the memory being anything other than 0.
The "RAM is based at zero" assumption is probably very deeply engraved in the design of the PPC code. I recommend not to touch this, as you might easily trigger all kinds of "interesting" phenomena ;-)
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And please: *NEVER* post HTML on this list.
Best regards,
Wolfgang Denk