Hi,
On Tue, 2015-09-08 at 17:51 +0530, Jagan Teki wrote:
On 8 September 2015 at 06:48, Chin Liang See clsee@altera.com wrote:
Ensure the intended SCLK frequency not exceeding the maximum frequency. If that happen, SCLK will set to maximum frequency.
Signed-off-by: Chin Liang See clsee@altera.com Cc: Dinh Nguyen dinguyen@opensource.altera.com Cc: Dinh Nguyen dinh.linux@gmail.com Cc: Marek Vasut marex@denx.de Cc: Stefan Roese sr@denx.de Cc: Vikas Manocha vikas.manocha@st.com Cc: Jagannadh Teki jteki@openedev.com Cc: Pavel Machek pavel@denx.de
drivers/spi/cadence_qspi.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 8c0f7dd..f430b5d 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -127,6 +127,11 @@ static int cadence_spi_set_speed(struct udevice *bus, uint hz) struct cadence_spi_priv *priv = dev_get_priv(bus); int err;
if (hz > plat->max_hz) {hz = plat->max_hz;puts("SF: Default to maximum supported SCLK frequency\n");This print mayn't require just assign plat->max_hz enough.
Sure, I can update that.
Thanks Chin Liang
Reviewed-by: Jagan Teki jteki@openedev.com
}/* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase);thanks!